z86230 ZiLOG Semiconductor, z86230 Datasheet - Page 27

• Manufacturer Part Number: z86230
• Description: Advanced Violence Blocking And Ntsc Line 21 Xds
• Manufacturer: ZiLOG Semiconductor

6.1.5 Interrupt Request Register
T
PS000400-TVC0499
ABLE
16. I
NTERRUPT
R
EQUEST
R
T
D
D
lines after the data line, and clears about 20 lines before the end of the field.
D
field. This bit sets during line 262 in Field 1 and line 524 in Field 2. This bit clears
about 2 lines before the end of the field.
D
The
D
D
The Line 21 Activity Register must be read to determine if XDS data is active.
D
N
to the appropriate bit in the Interrupt Request Register to clear the Interrupt. Writing a 1 to
Secondary Filter
All
Time Information
In Band Only
Content Advisory
VCR Information
Reserved
Reserved
Reserved
Notes:
Bit
R/W
EGISTERS
ABLE
OTE
0
1
2
3
4
5
6
-Res.
-DLE.
–EOF.
–dLOK.
-Res.
–dXDS.
-D
1. Setting this register to
2. The Time Information Only selection includes the Time of Day (TOD) and Local
3. VCR Information selects TOD, LTZ, Net ID, Local Call Letters, Impulse Capture,
SSR
:
7
through D
the Secondary Filter (bits D
XDS data are output (even Reserved and Undefined).
Time Zone (LTZ) packets.
Tape Delay, Composite 2, and Out-of-Band Channel Number packets for recovery.
-Res.
Except as noted for the case of D1 and D2 above, the master device must write a 1
15. XDS S
R
EGISTER
Reserved.
Reserved.
Active High, indicating that the data line has ended. This bit sets two
Active High, indicating that the video signal is currently at the end of a
must be read to determine the current state.
S
Active High, indicating that the state of the
Active High, indicating that a change in XDS activity has occurred.
UMMARY
Reserved.
4
Z86230—PRELIMINARY
(A
enables XDS data recovery for the Classes selected as qualified by
ECONDARY
DDRESS
R/W
res
7
R/W
= 06h)
res
00h
6
F
ILTER
5
–D
dXDS
turns XDS data recovery off. Setting bits D
R/W
7
S
5
). If Bits D
ETTINGS
R/W
res
4
0
–D
4
dLOK
are all set to 1, all Classes of
R/W
Filter Value (s0:s2)
3
LOCK
EOF
0h
1h
2h
3h
4h
5h
6h
7h
R
2
signal has changed.
C
ONTROL
DLE
1
R
R
EGISTERS
0
res
—
0
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