lm4312 National Semiconductor Corporation, lm4312 Datasheet - Page 12

• Manufacturer Part Number: lm4312
• Description: Mobile Pixel Link Two Mpl-2 , Rgb Display Differential Interface Serializer With Optional Dithering And Look Up Table
• Manufacturer: National Semiconductor Corporation

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Name
Command
Reserved, (Note 15)
LUT Red RAM
Address
LUT Red RAM Data
LUT Green RAM
Address
LUT Green RAM
Data
LUT Blue RAM
Address
LUT Blue RAM Data
Dither Configuration1
(Note 14)
Dither Configuration2
(Note 14)
Reserved
Configuration 3,
(Note 14)
Reserved, (Note 15)
Device Select
(Unlock/Lock)
Reserved, (Note 15)
LM4312 SPI Registers
Address
0x0C-
0x17-
0x0A
0x0B
0x7F
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x15
0x16
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
na
na
na
na
Description
Bit 0 = LUT Enable
Bit 4 = Special Register Access
For access to Registers 0x08, 0x09, 0x0B, the Special Register Access
bit must be unlocked. Must write all 8 bits.
Reserved
Red Address - This register contains the address for the next access to
the Red LUT RAM. After every read or write access to the Red Data
Register, this register auto-increments.
Red Data
Green Address - This register contains the address for the next access
to the Green LUT RAM. After every read or write access to the Green
Data Register, this register auto-increments.
Green Data
Blue Address - This register contains the address for the next access to
the Blue LUT RAM. After every read or write access to the Blue Data
Register, this register auto-increments.
Blue Data
Bit 0 - Dither Bypass
Bit 1 - DE INV
Bit 2 - VS INV
Bit 4 - Tempen0
Bit 5 - Tempen1
Bit 6 - Dith3 - Dither Amplitude
Dither Parameter
Reserved, Default value recommended.
Reserved
Bit 0 - Mode 24
Bit 1 - SER_PD
Bit[5:4] - Driver Level Select
Reserved
0xFF’h enables LM4312 SPI
All other values disables LM4312 SPI (0x00 to 0xFE)
Reserved
0’b = LUT Disabled, 1’b = LUT Enabled
0’b = SRA Locked, 1’b = SRA Unlocked
1’b = Bypass Dither, 0’b = Dither ON
1’b = Active Low DE, 0’b = Active High DE
Does not alter DE signal, dither block input only.
1’b = Active Low VS signal, 0’b = Active High VS signal.
Does not alter VS signal, dither block input only.
1’b = Transposed Dither Pattern,
0’b = Even and odd frames use same dither pattern
1’b = Temporal Dithering is Enabled, 0’b = Disabled
1’b = set to 3 bits, 0’b = set to 4 bits
1'b = 24-bit RGB Mode, 0'b= 18-bit RGB Mode
1'b = RESET the SER, 0'b = normal mode
00’b = VOD = 200mV
01’b = VOD = 150mV
12
Default
0xXX
0xXX
0xXX
0x00
0x00
0x00
0x00
0x65
0x67
0x00
0x00