lm4312 National Semiconductor Corporation, lm4312 Datasheet - Page 5

• Manufacturer Part Number: lm4312
• Description: Mobile Pixel Link Two Mpl-2 , Rgb Display Differential Interface Serializer With Optional Dithering And Look Up Table
• Manufacturer: National Semiconductor Corporation

PIXEL CLOCK (PCLK)
f
PCLK
t
t
SPI INTERFACE
f
f
t
t
t
t
t
t
t
t
t
t
PCLK
T
STOPpclk
SCLw
SCLr
s0
s1
h1
w1h
w1l
r
f
0H
h0
w2
Symbol
Recommended Input Timing Requirements (PCLK and SPI)
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise
specified.
Note 4: For IDD tests - input signal conditions are: (swing, edge, freq, DE = H, VS = L, HS = L, RGB Checkerboard Pattern: AAAAAA-555555)
Note 5: Total Supply Current Conditions: SER C
Note 6: Enable Time is a complete MPL-2 start up t1+t2+t3. See also Figure 8.
Note 7: Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality.
Note 8: Guaranteed functionally by the I
Note 9: MPL-2 serial link transition time is measured from 20% to 80 %.
Note 10: This is the minimum time that the PCLK needs to be held off for in order for the device to be reset. Once PCLK is reapplied, a PLL Lock is required and
start up sequence before video data is serialized.
Note 11: 1 UI is the serial data DD pulse width = 1 / 12xPCLK (18-bit mode), 1 UI is the serial data DD pulse width = 1 / 16xPCLK (24-bit mode)
Note 12: Specification is guaranteed by design or characterization
DC
Pixel Clock Frequency
Pixel Clock Duty Cycle
Input Transition Time
Clock Stop Gap
SPI_SCL Frequency
SPI_CSX Set Time
SI Set Time
SI Hold Time
SPI_SCL Pulse Width High
SPI_SCL Pulse Width Low
SPI_SCL Rise Time
SPI_SCL Fall Time
SI Hold Time
SPI_CSX Hold Time
SPI_CSX OFF Time
Parameter
DD
DDZ
=1.8V and T
parameter. See also Figure 9.
L
= 15 pF, TYP V
18-bit RGB Mode (6X)
24-bit RGB Mode (8X)
(Notes 7, 12)
(Notes 10, 12)
WRITE
READ
Figure 14
Figures 14, 15
Figure 14
A
= 25°C.
DD
= 1.8V.
Conditions
WRITE
READ
WRITE
READ
5
Min
100
30
60
30
30
35
60
35
60
30
65
5
5
2
4
Typ
>2
50
2
5
5
Max
6.67
30
30
70
10
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cycles
PCLK
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%