pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 22

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

Bits K1 and K0 of the control byte determine whether a CM or an indirect register access shall be
performed. When K1 and K0 are both logical 1, one of the indirect registers is accessed. For all
other combinations the connection memory is accessed.
Table 5
Decoding the K1 and K0 Bits
K1
0
0
1
1
In the case of a CM access the K1 and K0 bits also indicate the type of the access: One bit being
logical 1 indicates a write, both bits being logical 0 a read operation.
The same distinction function is performed by bit C0 of the control byte in the case of an indirect
register access. According to table 6 a high on C0 initiates a read, a low a write operation. The value
of the C1 bit is of no significance in this application. However to avoid future incompatibility
problems, it is strongly recommended to set C1 to logical 0.
The address byte holds the CM address for a connection memory access, for indirect register
access it indicates which one of the two indirect registers is accessed. A hexadecimal FE
addresses the configuration register, a hexadecimal FF
possible choices of indirect register accesses.
Table 6
Addressing of the Indirect Registers
K1
1
1
1
1
The data to be written to the different registers or the CM reside in the data byte. For CM accesses
not 8 but 10 bits are written into the selected location. The two bits in excess come from the C0 and
C1 bits of the control byte and are interpreted as the most significant bits of the data word. (D9 and
D8). Accordingly the 3 CM access instructions are interpreted as shown in table 7.
Semiconductor Group
K0
1
1
1
1
K0
0
1
0
1
C0
1
0
1
0
Address Byte (hex)
FE
FE
FF
FF
22
Accessed Register
CM
CM
CM
indirect register
H
the clock shift register. Table 6 lists all
Access
CFR read
CFR write
CSR read
CSR write
R/W
R
W
W
R or W
PEB 2045
PEF 2045
H