pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 25

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

2.3
A logical 1 in the CFS bit of the configuration register sets the PEx 2045 in standard mode (default
after power up). All modes from table 9 can be used. The space switch mode (MI1, MI0, MO1,
MO0 = 0
It has to be ensured that the data rate is not higher than the selected device clock (4096 or
8192 kHz).
In this application 512 channels per frame are written into the speech memory. Each one of them
can be connected to any output channel.
According to table 10 and table 14 and depending on the selected mode the least significant bits
of the connection memory address and data contain the logical pin numbers, the most significant
bits the time-slot number of the output and input channels.
The following example explains the programming sequence.
Time-slot 7 of the incoming 8192-kbit/s input line IN14 shall be connected to time-slot 6 of the output
line OUT 5 of an 2048-kbit/s system. According to table 10 in 8192-kbit/s systems the input line
IN14 is the logical input line 2. Output line number and logical output number are identical to one
another.
Therefore the following byte sequence on the data bus has to be used to program the CM properly
(see table 14):
00010000
00011110
00110101
The frame, for all input channels, starts with the rising edge of the SP signal. The frame for all output
channels begins two
before the falling SP edge. The period of time between the rising and the falling edge of the SP
pulse should be
t
N is an user defined integer. By varying N,
an example using N = 2 refer to figure 14.
Semiconductor Group
SPH
= (2 + N
= (1 + N
Standard Configuration
H
) is a special mode and will be covered in chapter 2.5.
4)
2)
t
t
CP8
CP4
t
CP8
(with 8192-kHz device clock) or one
(0
N
255)
t
SPH
can be varied in 2048-kHz clock period steps. For
25
t
CP4
period (4096-kHz device clock)
PEB 2045
PEF 2045