pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 41

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

Configuration Register Access (CFR)
Access: Read or write indirect address FE
For a read access the bit 0 of the control byte must be set to logical 1 and for a write access to
logical 0.
Value after power up or software reset: FF
CPS …
CFS …
Clock Shift Register Access (CSR)
Access: Read or write at indirect address FF
For a read access the bit 0 of the control byte has to be set to logical 1 and for a write access to
logical 0.
The value after power is 00
RS2 … RS0 … Receive clock Shift, bits 2 – 0. The receive data stream is shifted in bit period
RRE …
XS0 … XS2 … Transmit clock Shift, bits 2 – 0. The transmitted data stream is shifted as shown
XFE …
Data stream manipulation according to these register entries only affects the system interface and
only in the primary access configuration. The frame structure can be moved relative to the SP slope
by up to 7 clock periods in half clock period steps. This register can hold non-zero values only for a
CFR:CFS value of logical 0. Figure 21 illustrates the clock shifting facility.
Semiconductor Group
DB 7
DB 7
1
RS2
Clock Period Select: Device clock is set to 8192 kHz (logical 1) or 4096 kHz (logical 0).
Configuration Select: The PEx 2045 works in either the primary access configuration
(logical 0) or in standard configuration (logical 1). Setting this bit to logical 1 resets the
CSR to 00
steps as shown in figure 21.
Receive with Rising Edge. The data is sampled with the falling (RRE = 0) or rising
edge (RRE = 1) of the data equivalent clock (see figure 21).
in figure 21.
Transmit with Falling Edge; data is transmitted with the rising (XFE = 0) or falling
edge (XFE = 1) of the device clock.
H
.
H
.
H
H
H
.
41
1
RS1
DB 0
DB 0
PEB 2045
PEF 2045