m34116 STMicroelectronics, m34116 Datasheet - Page 3

• Manufacturer Part Number: m34116
• Description: Pcm Conference Call And Tone Generation Circuit
• Manufacturer: STMicroelectronics

PIN DESCRIPTION
6 to 13
DIP
N
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
o
13 to 16
9 to 11,
PLCC
N
7,
17
18
19
20
21
23
24
25
27
28
2
3
4
5
6
1
o
CLOCK Master Clock input pin. Typ. operating Frequencies are:
IN PCM PCM input pin. The max bit rate is 4096Kbits/s. The first bit of the first cahnnel is found at
RESET Master reset input pin. This pin is active low and must be used at the very beginning after
SYNC
A/MU
D0 to
PCM
OUT
VDD
C/D
WR
Vss
Pin
TD
OS
CS
RD
EC
TF
D7
M116 operating mode only. Tone Duration input pin. When TD = 1, a PCM coded tone
(instead of PCM data) is sent out to all channels enabled by the IT bit. TD is latched by
the SYNC signal so that all channels have the same tone during the same number of
frames. TD = 0 for normal operation.
M116 operating mode only. Tone Frequency input pin. When TF = 1, the tone amplitude
is high. When TF = 0, the tone amplitude is low. TF is latched by SYNC. The PCM coded
tone level corresponds to 1/10 of the full scale. For M34116 operating mode: Melody
waveform select input pin. When TF = 1, the PCM output of the melody represents a
square wave. When TF = 0, it represents a sine wave. In both cases, the rms level is the
same and is equal to – 6 dBm0 if no attenuation or gain is programmed.
power up to initialize the device or when switching from A law to Mu law. The Internal
initialization routine takes 2 time frames starting from the rising edge of RESET. During
this initialization time, all data bus and PCM output are pulled to a high impedance state.
Overflow Signalling output pin. When OS = 0 one conference is in overflow. This signal is
anticipated over half time slot with respect to the output channel involved in the conference in
overflow. Example: if output channel 4 is one of the parties of one conference in
overflow, OS = 0 during the second half of the time slot corresponding to output channel 3
and during the first half of the time slot corresponding to output channel 4.
PCM output pin. The bit rate is 4096Kbits/s max. The sign bit is the first bit of the serial
sequence. The first bit of the first channel is found at the rising edge of the CLOCK signal
preceding the rising edge of the SYNC signal. The output buffer is open drain to allow for
multiple connections.
Bidirectional Data bus pins. Data and instructions are transferred to or from the
microprocessor. D0 is the Least Significant Bit. The bus is tristate when RESET is low
and/or CS is high.
+5V Supply input. 100nF decoupling capacitor recommended.
Control Data input pin. In a write operation C/D = 0 qualifies any bus content as data
while C/D = 1 qualifies it as an opcode. For M116 operating mode only: in a read
operation, the overflow information of the first eight conferences is selected by C/D = 0,
the overflow of the last two conferences and the status by C/D = 1.
Chip Select input pin. When CS = 0, data and instructions can be transferred to or from
the external microprocessor and when CS = 1 the data bus is in tristate.
Read control input pin. When RD = 0, read operation is performed. When match
conditions for the opcode exists, data is transferred to the external microprocessor on the
falling edge of RD.
Write control input pin. Instructions and opcode from the external microprocessor are
latched on the rising edge of WR.
Synchronization input pin. The rising edge of CLOCK preceding the rising edge of SYNC
corresponds to the first bit of the first channel except for PCM frame of 1544Kbits/s. In
this case, it corresponds to the Extra bit (193th).
Both M34116 an M116 operating modes are possible up to 4.096MHz.
At 8.192MHz only M34116 operating mode is possible.
External Clock output pin. This pin provides the master clock for the Digital Switching
Matrix (M3488). Normally it is the same signal as applied to the CLOCK input (pin 20).
When the Extra bit is selected with the instruction 5, the first two periods of the master
clock are canceled in order to allow the operation of the M34116 and the DSM with PCM
frame with Extra bit (e.g. 193 bit/frame with PCM I/O of 1544Kbits/s).
the second rising edge of the CLOCK signal following the rising edge of the SYNC signal.
If Extra bit is selected, then the first bit is shifted by two CLOCK periods.
A Law or MU Law select pin. When A/MU = 1, A Law is selected. When A/MU = 0, MU Law is
selected. The law selection must be done before initializing the device using the RESET pin.
Ground.
3.072MHz for 24 PCM channels frame (192 bit/frame)
3.088MHz for 24 PCM channels frame with extra bit (193 bit/frame)
4.096MHz for 32 PCM channels frame (256 bit/frame)
8.192MHz for 64 PCM channels frame (512 bit/frame)
Function
M34116
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