pnx8510 NXP Semiconductors, pnx8510 Datasheet - Page 38

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pnx8510

Manufacturer Part Number
pnx8510
Description
Analog Companion Chip
Manufacturer
NXP Semiconductors
Datasheet

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7.6.1 Clocks video submodule
7.6.2 Clocks audio submodule
The PNX8510/11 video clocks are used to create two internal clocks: one for
operating the video input interface (clk_dv1_if, clk_dv2_if), and one for operating the
main video processing pipeline (clk_dv1_proc, clk_dv2_proc).
The audio interface normally operates in slave mode (over-sampling clock, word
select and bit clock are provided from the externally connected I
the PNX8510/11 can be operated in master mode. This mode only requires the
over-sampling clock to be provided. The bit clock and the word select signals are
subdivided from the over-sampling clock and provided to the chip pins.
Remark: Both video clocks (DV_CLK1 and DV_CLK2) and an audio clock
(I2S_AOS1_CLK) have to be connected to the device for proper functioning of the I
programming interface. These clocks must be provided before the reset line
(RESET_N) is pulled high to ensure correct initialization of the device. For more
information refer to
If the two video pipelines are sourced by only one video input interface operating in
sliced mode, both video pipelines must receive the same input clock originating from
the same sliced data source.
The generation of the various clock signals needed for video pipelines takes place in
the clocks video module.
configuration registers for the clocks module can be found in
The input clocks for the audio block are generated in the clocks audio submodule.
Figure 30
Fig 29. Clocks video submodule
shows a block diagram for this submodule
dv_clk
sel_v
Rev. 04 – 12 January 2004
Section
Figure 29
CLOCK DIVIDER
CLOCK DIVIDER
DE-GILITCHER
DE-GILITCHER
10.4.
&
&
shows a block diagram of this module. The
clocks_sel
div by 1, 2, 3 or 4
clocks_sel
div by 1, 2, 3 or 4
dv_clk
dv_clk
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
test
test
PNX8510/11
Analog companion chip
clk_dv_if_out
clk_dv_proc_out
Section
2
S master). However
MDB657
8.2.
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2
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