24lc41 Microchip Technology Inc., 24lc41 Datasheet - Page 3

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24lc41

Manufacturer Part Number
24lc41
Description
1k/4k 2.5v Dual Mode, Dual Port I 2 C? Serial Eeprom
Manufacturer
Microchip Technology Inc.
Datasheet

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TABLE 1-2:
 2004 Microchip Technology Inc.
Clock frequency
(DSCL and MSCL)
Clock high time
(DSCL and MSCL)
Clock low time
(DSCL and MSCL)
DSCL, DSDA, MSCL and
MSDA rise time
DSCL, DSDA, MSCL and
MSDA fall time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
Output fall time from V
min to V
Input filter spike
suppression (DSCL, DSDA,
MSCL and MSDA pins)
Write cycle time
DDC Monitor Port Transmit-Only Mode Parameters
Output valid from VCLK/
DWP
VCLK/DWP high time
VCLK/DWP low time
Mode transition time
Transmit-only power-up
time
Endurance
Note 1:
2:
3:
4:
IL
Parameter
max
Not 100% tested. C
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop
conditions.
The combined T
noise and spike suppression. This eliminates the need for a T
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ model which can be obtained from our web site.
AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER
ACCESS PORTS)
DDC Monitor Port (Bidirectional Mode) and Microcontroller Access Port
IH
SP
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Symbol
and V
B
SU
SU
SU
AA
OF
SP
CLK
HIGH
LOW
R
F
HD
HD
BUF
WR
VAA
VHIGH
VLOW
VHZ
VPU
= total capacitance of one bus line in pF.
:
:
:
:
:
STA
DAT
STO
STA
DAT
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
Standard Mode
4000
4700
4000
4700
4000
4700
4000
4700
Min
250
1M
0
0
1000
3500
2000
Max
100
300
250
500
50
10
Vcc = 4.5 - 5.5V
20 + .1
1300
1300
1300
Min
600
600
600
100
600
600
1M
C
Fast Mode
0
0
B
1000
Max
400
300
300
900
250
500
50
10
I
specification for standard operation.
cycles
Units
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
Start condition
(Note 2)
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
(Note 3)
Byte or Page mode
25°C, Vcc = 5.0V, Block
mode (Note 4)
24LC41
Remarks
B
DS21140F-page 3
100 pF

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