24lc41 Microchip Technology Inc., 24lc41 Datasheet - Page 6

• Manufacturer Part Number: 24lc41
• Description: 1k/4k 2.5v Dual Mode, Dual Port I 2 C? Serial Eeprom
• Manufacturer: Microchip Technology Inc.

24LC41
3.0
Characteristics for the bidirectional bus are identical for
both the DDC Monitor Port (in Bidirectional mode) and
the Microcontroller Access Port The following bus
protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Both data and clock lines remain high.
3.2
A high-to-low transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Start condition. All commands must be preceded by a
Start condition.
3.3
A low-to-high transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is high determines a
Stop condition. All operations must be ended with a
Stop condition.
3.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first in first
out fashion.
DS21140F-page 6
is not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
BIDIRECTIONAL BUS
CHARACTERISTICS
Bus not Busy (A)
Start Data Transfer (B)
Stop Data Transfer (C)
Data Valid (D)
3.5
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
DSDA or MSDA line during the Acknowledge clock
pulse in such a way that the DSDA or MSDA line is
stable low during the high period of the acknowledge
related clock pulse. Of course, setup and hold times
must be taken into account. A master must signal an
end of data to the slave by not generating an Acknowl-
edge bit on the last byte that has been clocked out of
the slave. In this case, the slave must leave the data
line high to enable the master to generate the Stop
condition.
3.6
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code. This
control code is set as 1010 for both read and write oper-
ations and is the same for both the DDC Monitor Port
and Microcontroller Access Port. The next three bits of
the control byte are block select bits (B1, B2 and B0).
All three of these bits are don’t care bits for the DDC
Monitor Port. The B2 and B1 bits are don’t care bits for
the Microcontroller Access Port, and the B0 bit is used
by the Microcontroller Access Port to select which of
the two 256 word blocks of memory are to be accessed
(Figure 3-4). The B0 bit is effectively the Most Signifi-
cant bit of the word address. The last bit of the control
byte defines the operation to be performed. When set
to one, a read operation is selected; when set to zero,
a write operation is selected. Following the Start condi-
tion, the device monitors the DSDA or MSDA bus
checking the device type identifier being transmitted,
upon a 1010 code the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the device will select a read or a
write operation. The DDC Monitor Port and Microcon-
troller Access Port can be accessed simultaneously
because they are completely independent of one
another.
Operation
Note:
Read
Write
Acknowledge
Device Addressing
The microcontroller access port and the
DDC Monitor Port (in Bidirectional mode)
will not generate any Acknowledge bits if
an internal programming cycle is in
progress.
Control Code
1010
1010
 2004 Microchip Technology Inc.
Chip Select
XXB0
XXB0
R/W
1
0