24lc41 Microchip Technology Inc., 24lc41 Datasheet - Page 4

• Manufacturer Part Number: 24lc41
• Description: 1k/4k 2.5v Dual Mode, Dual Port I 2 C? Serial Eeprom
• Manufacturer: Microchip Technology Inc.

24LC41
2.0
2.1
The DDC Monitor Port operates in two modes, the
Transmit-only mode and the Bidirectional mode. There
is a separate 2-wire protocol to support each mode,
each having a separate clock input and sharing a
common data line (DSDA). The device enters the
Transmit-only mode upon power-up. In this mode, the
device transmits data bits on the DSDA pin in response
to a clock signal on the VCLK/DWP pin. The device will
remain in this mode until a valid high-to-low transition is
placed on the DSCL input. When a valid transition on
DSCL is recognized, the device will switch into the
Bidirectional mode. The only way to switch the device
back to the Transmit-only mode is to remove power
from the device.
2.2
The device will power-up in the Transmit-only mode.
This mode supports a unidirectional 2-wire protocol for
transmission of the contents of the memory array. This
device requires that it be initialized prior to valid data
being sent in the Transmit-only mode (Section 2.3
FIGURE 2-1:
FIGURE 2-2:
DS21140F-page 4
VCLK/DWP
VCLK/DWP
FUNCTIONAL DESCRIPTION
DDC Monitor Port
Transmit-Only Mode
DSDA
DSCL
SDA
SCL
V
CC
TRANSMIT-ONLY MODE
DEVICE INITIALIZATION
High-impedance for 9 clock cycles
T
VAA
T
T
1
VPU
VHIGH
Bit 1 (LSB)
T
VLOW
2
T
VAA
Null Bit
“Initialization Procedure”).
transmitted on the DSDA pin in 8-bit bytes, each
followed by a ninth, null bit (Figure 2-1). The clock
source for the Transmit-only mode is provided on the
VCLK/DWP pin, and a data bit is output on the rising
edge on this pin. The eight bits in each byte are trans-
mitted by Most Significant bit first. Each byte within the
memory array will be output in sequence. When the last
byte in the memory array is transmitted, the output will
wrap around to the first location and continue. The
Bidirectional mode Clock (DSCL) pin must be held high
for the device to remain in the Transmit-only mode.
2.3
After V
Transmit-only mode. Nine clock cycles on the VCLK/
DWP pin must be given to the device for it to perform
internal sychronization. During this period, the DSDA
pin will be in a high-impedance state. On the rising
edge of the tenth clock cycle, the device will output the
first valid data bit which will be the Most Significant bit
of a byte. The device will power-up at an indeterminate
byte address (Figure 2-2).
8
CC
Initialization Procedure
has stabilized, the device will be in the
9
Bit 1 (MSB)
 2004 Microchip Technology Inc.
T
VAA
10
In this mode, data is
Bit 8
T
VAA
11
Bit 7
Bit 7