at88sa102s ATMEL Corporation, at88sa102s Datasheet - Page 13

• Manufacturer Part Number: at88sa102s
• Description: Cryptoauthentication
• Manufacturer: ATMEL Corporation

3.4.1. IO Timeout
3.4.2. Synchronization Procedures
3.5.
3.6.
8584A–SMEM–03/09
After a leading transition for any data token has been received, CryptoAuthentication will expect another token to be
transmitted within a t
CryptoAuthentication assumes that the synchronization with the host is lost and transitions to a sleep state.
After CryptoAuthentication receives the last bit of a command block, this timeout circuitry is disabled. If the command is
properly formatted, then it is re-enabled with the first transmit token that occurs after t
in the command, then it is re-enabled with the first transmit token that occurs after t
In order to limit the active current if CryptoAuthentication is inadvertently awakened, the IO timeout is also enabled
when CryptoAuthentication wakes up. If the first token does not come within the t
CryptoAuthentication will go back to sleep without performing any operations.
When the system and CryptoAuthentication fall out of synchronization, the system will ultimately end up sending a
transmit flag which will not generate a response from CryptoAuthentication. The system should implement its own
timeout which waits for t
the system should send a Wake token and after t
resynchronization was successful.
It may be possible that the system does not get the 0x11 code from CryptoAuthentication for one of the following
reasons:
1.
2.
3.
Watchdog Failsafe
After the Wake token has been received by CryptoAuthentication, a watchdog counter is started within the chip. After t
WATCHDOG
whether some IO transmission is in progress. There is no way to reset the counter other than to put the chip to sleep
and wake it up again.
This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state
machines of CryptoAuthentication including any IO synchronization issue, power consumption will fall to the low sleep
level automatically.
Byte & Bit Ordering
CryptoAuthentication is a little-endian chip:
• All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order
• Data is transferred to/from CryptoAuthentication least significant bit first on the bus.
• In this document, the most significant bit and/or byte appears towards the left hand side of the page.
received.
The system did not wait a full t
interpreted the Wake token and Transmit flag as data bits. Recommended resolution is to wait twice the t
delay and re-issue the Wake token.
CryptoAuthentication went into the sleep mode for some reason while the system was transmitting data. In this
case, CryptoAuthentication will interpret the next data bit as a wake token, but ignore some of the subsequently
transmitted bits during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be
interpreted as a legal flag, though the following bytes would not be interpreted as a legal command due to an
incorrect count or the lack of a correct CRC. Recommended resolution is to wait the t
the Wake token.
There is some internal error condition within CryptoAuthentication which will be automatically reset after a
t
the IO pin idle for this interval and issue the Wake token.
WATCHDOG
, the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or
interval, see below. There is no way to externally reset CryptoAuthentication – the system should leave
TIMEOUT
TIMEOUT
interval. If the leading edge of the next token is not received within this period of time,
during which time CryptoAuthentication should go to sleep automatically. At this point,
TIMEOUT
delay with the IO signal idle in which case CryptoAuthentication may have
WLO
+ t
WHI
, a Transmit token. The 0x11 status indicates that the
AT88SA102S [Preliminary]
PARSE
PARSE
.
TIMEOUT
+ t
EXEC
TIMEOUT
. If there is an error
delay and re-issue
interval, then
TIMEOUT
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