m58lt256jsb STMicroelectronics, m58lt256jsb Datasheet - Page 88

• Manufacturer Part Number: m58lt256jsb
• Description: 256 Mbit 16 Mb 16, Multiple Bank, Multilevel, Burst 1.8 V Supply, Secure Flash Memories
• Manufacturer: STMicroelectronics

Common Flash interface
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Table 44.
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Tables
3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not
(P+40)h = 14Ah 03h
(P+41)h = 14Bh 00h
(P+42)h = 14Ch 80h
(P+43)h = 14Dh 00h
(P+44)h = 14Eh 64h
(P+45)h = 14Fh 00h
(P+46)h = 150h 02h
(P+47)h = 151h 03h
(P+48)h = 152h
(P+49)h = 153h
advantageous in a multiplexed device.
M58LT256JST
Offset
Bank and erase block region 2 information (continued)
Data
(P+43)h = 153h
(P+48)h = 152h
M58LT256JSB
Offset
Data
Bank region 2 Erase Block type 2 information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n × 256 = number of bytes in erase
block region
Minimum block erase cycles × 1000
Bank region 2 (Erase Block Type 2): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
Bank region 2 (Erase Block type 2): page mode
and synchronous mode capabilities (defined in
Table
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
Feature space definitions
Reserved
Bank region 2 (Erase Block type 2)
29
to 34.
41)
M58LT256JST, M58LT256JSB
Description