hip6303cbz-t Intersil Corporation, hip6303cbz-t Datasheet - Page 12

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hip6303cbz-t

Manufacturer Part Number
hip6303cbz-t
Description
Microprocessor Core Voltage Regulator Multiphase Buck Pwm Controller
Manufacturer
Intersil Corporation
Datasheet
Droop, Selection of R
The average of the currents detected through the R
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for R
current creates a voltage drop across R
increases the apparent V
current, causing the system to decrease V
balance at the FB pin. This is the desired “droop” voltage
used to maintain V
conditions.
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
occur at the leading and trailing edges of the load transient.
In order to fully utilize the output-voltage tolerance range, the
output voltage is positioned in the upper half of the range
when the output is unloaded and in the lower half of the
range when the controller is under full load. This droop
compensation allows larger transient voltage deviations and
thus reduces the size and cost of the output filter
components.
R
the normal full load current 50 A applied through the R
resistor (or at a different full load current if adjusted as under
“Over-Current, Selecting R
R
For a Vdroop of 80mV, R
A resistor from the feedback pin to ground raises the output
voltage above VID when the output is unloaded. The offset
resistor, (R
desired no-load offset, (VOS).
R
Current Balancing
The detected currents are also used to balance the channel
currents.
Each channel’s current is compared to the average of all
channel currents, and the difference is used to create an
offset in that channel’s PWM comparator. The offset is in a
direction to reduce the imbalance.
The balancing circuit can not make up for a difference in
r
higher r
reduced.
Figures 8 and 9 show the inductor current of a two channel
system without and with current balancing.
Inductor Current
The inductor current in each channel of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of channels (I
and a sawtooth current, (i
The sawtooth component is dependent on the size of the
DS(ON)
IN
IN
os
should be selected to give the desired “droop” voltage at
= Vdroop / 50 A
= R
DS(ON)
IN
between synchronous rectifiers. If a FET has a
x VID / VOS
os
), is selected based on R
, the current through that channel will be
CORE
IN
CORE
within limits under transient
IN
PK-PK
ISEN
= 1.6k
12
” above).
voltage with increasing load
) resulting from switching.
IN
IN
and the amount of
IN
. This drop
CORE
, so the average
to maintain
ISEN
LT
ISEN
/ n),
HIP6303
inductors, the switching frequency of each channel, and the
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
i
Where: V
Example: For V
Then i
PK-PK
FIGURE 8. TWO CHANNEL MULTIPHASE SYSTEM WITH
FIGURE 9. TWO CHANNEL MULTIPHASE SYSTEM WITH
25
20
15
10
5
0
PK-PK
= (V
25
20
15
10
5
0
CORE
IN
F
V
= 4.3A
SW
CURRENT BALANCING DISABLED
CURRENT BALANCING ENABLED
x V
IN
L = value of the inductor
CORE
F
CORE
= DC value of the output or V
= DC value of the input or supply voltage
= switching frequency
V
SW
IN
L = 1.3 H,
= 1.6V,
= 12V,
= 250kHz,
- V
CORE
2
) / (L x F
SW
x V
ID
voltage
IN
)

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