hip6303cbz-t Intersil Corporation, hip6303cbz-t Datasheet - Page 15

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hip6303cbz-t

Manufacturer Part Number
hip6303cbz-t
Description
Microprocessor Core Voltage Regulator Multiphase Buck Pwm Controller
Manufacturer
Intersil Corporation
Datasheet
Output Inductor Selection
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Small inductors in a multi-phase converter reduces
the response time without significant increases in total ripple
current.
The output inductor of each power channel controls the
ripple current. The control IC is stable for channel ripple
current (peak-to-peak) up to twice the average current. A
single channel’s ripple current is approximately:
The current from multiple channels tend to cancel each other
and reduce the total ripple current. Figure 12 gives the total
ripple current as a function of duty cycle, normalized to the
parameter
the total ripple current from the number of channels and the
duty cycle, multiply the y-axis value by
Small values of output inductance can cause excessive power
dissipation. The HIP6303 is designed for stable operation for
ripple currents up to twice the load current. However, for this
condition, the RMS current is 115% above the value shown in
the following MOSFET Selection and Considerations section.
With all else fixed, decreasing the inductance could increase
the power dissipated in the MOSFETs by 30%.
Input Capacitor Selection
The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current required for a
multi-phase converter can be approximated with the aid of
Figure 13.
I
=
V
------------------------------- -
1.0
0.8
0.6
0.4
0.2
IN
F
FIGURE 12. RIPPLE CURRENT vs DUTY CYCLE
0
SW
0
V
Vo
OUT
L
3 CHANNEL
LxF
V
--------------- -
0.1
V
OUT
4 CHANNEL
IN
SW
DUTY CYCLE (V
at zero duty cycle. To determine
0.2
15
SINGLE
CHANNEL
2 CHANNEL
0.3
O
Vo
/V
IN
)
LxF
0.4
SW
.
0.5
HIP6303
First determine the operating duty ratio as the ratio of the
output voltage divided by the input voltage. Find the Current
Multiplier from the curve with the appropriate power
channels. Multiply the current multiplier by the full load
output current. The resulting value is the RMS current rating
required by the input capacitor.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors should be
placed very close to the drain of the upper MOSFET to
suppress the voltage induced in the parasitic circuit
impedances.
For bulk capacitance, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the following
equations). The conduction losses are the main component
of power dissipation for the lower MOSFETs, Q2 and Q4 of
Figure 1. Only the upper MOSFETs, Q1 and Q3 have
significant switching losses, since the lower device turns on
and off into near zero voltage.
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFETs body diode. The gate-charge losses are
0.5
0.4
0.3
0.2
0.1
FIGURE 13. CURRENT MULTIPLIER vs DUTY CYCLE
0
0
4 CHANNEL
0.1
DUTY CYCLE (V
0.2
3 CHANNEL
SINGLE
CHANNEL
0.3
O
/V
IN
2 CHANNEL
)
0.4
0.5

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