W83627F Information Storage Devices, Inc, W83627F Datasheet - Page 91

• Manufacturer Part Number: W83627F
• Description: LPC Interface I/o Plus Kbc, Game Port, Midi Port
• Manufacturer: Information Storage Devices, Inc

CRF0 (Default 0x80)
4.7 Logical Device 6 (CIR)
CR30 (Default 0x00)
CR60, CR 61 (Default 0x00, 0x00)
CR70 (Default 0x00)
4.8 Logical Device 7 (Game Port and MIDI Port and GPIO Port 1)
CR30 (Default 0x00)
CR60, CR 61 (Default 0x02, 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise)
These two registers select CIR I/O base address [0x100:0xFF8] on 8 byte boundary.
These two registers select the Game Port base address [0x100:0xFFF] on 1 byte boundary.
Bit 7 - 6 : KBC clock rate selection
Bit 5 - 3 : Reserved.
Bit 2
Bit 1
Bit 0
Bit 7 - 1 : Reserved.
Bit 0
Bit 7 - 4 : Reserved.
Bit [3:0] : These bits select IRQ resource for CIR.
Bit 7 - 3 : Reserved
Bit 2
Bit 1
Bit 0
= 00 Select 6MHz as KBC clock input.
= 01 Select 8MHz as KBC clock input.
= 10 Select 12Mhz as KBC clock input.
= 11 Select 16Mhz as KBC clock input.
(W83627HF/F-AW can support these 4 kinds of clock input, but W83627HF/F-PW only
support 12MHz clock input)
= 0 Port 92 disable.
= 1 Port 92 enable.
= 0 Gate20 software control.
= 1 Gate20 hardware speed up.
= 0 KBRST software control.
= 1 KBRST hardware speed up.
= 1 Activates the logical device.
= 0 Logical device is inactive.
=1 Only MIDI Port Active. (Only For J version)
=0 Only MIDI Port Disable.
=1 Only Game Port Active. (Only For J version)
=0 Only Game Port Disable.
= 1 Activate Game Port, MIDI Port, and GPIO Function.
= 0 Game Port and MIDI Port is inactive.
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Publication Release Date:November 2002
W83627HF/F
Revision 2.0