lpc2364 NXP Semiconductors, lpc2364 Datasheet - Page 16

• Manufacturer Part Number: lpc2364
• Description: Single-chip 16-bit/32-bit Microcontrollers; Up To 512 Kb Flash With Isp/iap, Ethernet, Usb 2.0, Can, And 10-bit Adc/dac
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2364_66_68_3
Product data sheet
7.2 On-chip flash programming memory
7.3 On-chip SRAM
7.4 Memory map
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The LPC2364/66/68 incorporate a 128 kB, 256 kB, and 512 kB flash memory system
respectively. This memory may be used for both code and data storage. Programming of
the flash memory may be accomplished in several ways. It may be programmed In
System via the serial port (UART0). The application program may also erase and/or
program the flash while the application is running, allowing a great degree of flexibility for
data storage field and firmware upgrades.
The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to
allow it to operate at SRAM speeds of 72 MHz.
The LPC2364/66/68 provides a minimum of 100000 write/erase cycles and 20 years of
data retention.
The LPC2364/66/68 includes a SRAM memory of 8 kB, 32 kB, and 32 kB respectively,
reserved for the ARM processor exclusive use. This RAM may be used for code and/or
data storage and may be accessed as 8 bits, 16 bits, and 32 bits.
A 16 kB SRAM block serving as a buffer for the Ethernet controller and an 8 kB SRAM
associated with the USB device can be used both for data and code storage, too. The
2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered
and retains the content in the absence of the main power supply.
The LPC2364/66/68 memory map incorporates several distinct regions as shown in
Figure
In addition, the CPU interrupt vectors may be remapped to allow them to reside in either
flash memory (default), boot ROM, or SRAM (see
•
A 16-bit Thumb set
4.
Rev. 03 — 20 December 2007
Section
LPC2364/66/68
7.25.6).
Fast communication chip
© NXP B.V. 2007. All rights reserved.
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