lpc2364 NXP Semiconductors, lpc2364 Datasheet - Page 30

• Manufacturer Part Number: lpc2364
• Description: Single-chip 16-bit/32-bit Microcontrollers; Up To 512 Kb Flash With Isp/iap, Ethernet, Usb 2.0, Can, And 10-bit Adc/dac
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2364_66_68_3
Product data sheet
7.24.4.1 Idle mode
7.24.4.2 Sleep mode
7.24.4 Power control
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of Reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the wake-up Timer.
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin
code execution. When power is applied to the chip, or when some event caused the chip
to exit Power-down mode, some time is required for the oscillator to produce a signal of
sufficient amplitude to drive the clock logic. The amount of time depends on many factors,
including the rate of V
electrical characteristics (if a quartz crystal is used), as well as any other external circuitry
(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
The LPC2364/66/68 supports a variety of power control features. There are three special
modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode.
The CPU clock rate may also be controlled as needed by changing clock sources,
reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a
trade-off of power versus processing speed based on application requirements. In
addition, Peripheral Power Control allows shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Each of the peripherals
has its own clock divider which provides even better power control.
The LPC2364/66/68 also implements a separate power domain in order to allow turning
off power to the bulk of the device while maintaining operation of the RTC and a small
SRAM, referred to as the Battery RAM.
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The
processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Sleep mode and the logic levels of chip pins remain static. The
output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The
32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The CCLK and
USB clock dividers automatically get reset to zero.
The Sleep mode can be terminated and normal operation resumed by either a Reset or
certain specific interrupts that are able to function without clocks. Since all dynamic
operation of the chip is suspended, Sleep mode reduces chip power consumption to a
very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up.
Rev. 03 — 20 December 2007
DD(3V3)
ramp (in the case of power on), the type of crystal and its
LPC2364/66/68
Fast communication chip
© NXP B.V. 2007. All rights reserved.
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