lpc2361 NXP Semiconductors, lpc2361 Datasheet - Page 14

• Manufacturer Part Number: lpc2361
• Description: Single-chip 16-bit/32-bit Mcu; Up To 128 Kb ?ash With Isp/iap, Ethernet, Usb 2.0 Device/host/otg, Can, And 10-bit Adc/dac
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2361_62_3
Product data sheet
7.2 On-chip flash programming memory
7.3 On-chip SRAM
7.4 Memory map
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The LPC2361/62 incorporate a 64 kB and 128 kB flash memory system respectively. This
memory may be used for both code and data storage. Programming of the flash memory
may be accomplished in several ways. It may be programmed In System via the serial port
(UART0). The application program may also erase and/or program the flash while the
application is running, allowing a great degree of flexibility for data storage field and
firmware upgrades.
The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to
allow it to operate at SRAM speeds of 72 MHz.
The LPC2361/62 provides a minimum of 100000 write/erase cycles and 20 years of data
retention.
The LPC2361/62 include SRAM memory of 8 kB (LPC2361) or 32 kB (LPC2362),
reserved for the ARM processor exclusive use. This RAM may be used for code and/or
data storage and may be accessed as 8 bits, 16 bits, and 32 bits.
A 16 kB SRAM block serving as a buffer for the Ethernet controller (available as general
purpose SRAM for the LPC2361) and an 8 kB SRAM used by the GPDMA controller or
the USB device can be used both for data and code storage. The 2 kB RTC SRAM can be
used for data storage only. The RTC SRAM is battery powered and retains the content in
the absence of the main power supply.
The LPC2361/62 memory map incorporates several distinct regions as shown in
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The standard 32-bit ARM set
A 16-bit Thumb set
Rev. 03 — 11 November 2008
Single-chip 16-bit/32-bit MCU
LPC2361/62
© NXP B.V. 2008. All rights reserved.
Figure
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3.