lpc2361 NXP Semiconductors, lpc2361 Datasheet - Page 24

• Manufacturer Part Number: lpc2361
• Description: Single-chip 16-bit/32-bit Mcu; Up To 128 Kb ?ash With Isp/iap, Ethernet, Usb 2.0 Device/host/otg, Can, And 10-bit Adc/dac
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2361_62_3
Product data sheet
7.19.1 Features
7.19 General purpose 32-bit timers/external event counters
7.20 Pulse width modulator
The LPC2361/62 include four 32-bit Timer/Counters. The Timer/Counter is designed to
count cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. The Timer/Counter also includes two capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt.
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2361/62. The Timer is designed to count
cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features, and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires three
non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge
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Configurable word select period in master mode (separately for I
Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected to
the GPDMA block.
Controls include reset, stop and mute options separately for I
A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Counter or Timer operation.
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Rev. 03 — 11 November 2008
Single-chip 16-bit/32-bit MCU
LPC2361/62
2
S input and I
2
S input and output).
© NXP B.V. 2008. All rights reserved.
2
S output.
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