mc94mx21 Freescale Semiconductor, Inc, mc94mx21 Datasheet

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... Introduction Freescale’s i.MX family of microprocessors has demonstrated leadership in the portable handheld market. Building on the success of the MX (Media Extensions) series, the i.MX21 (MC94MX21) provides a leap in performance with an ARM926EJ-S microprocessor core that provides accelerated Java support in addition to highly integrated system functions. The i.MX21 device specifically addresses the needs of ...

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... MMU I Cache D Cache Bus Control Internal Control Memory Control Enhanced Multimedia Accelerator (eMMA) Pre- and Post- Processing Video Accelerator Figure 1. i.MX21 Functional Block Diagram MC94MX21 Technical Data, Rev. 1.4 Connectivity CSPI x 3 SSI Audio Mux UART x 4 1-WIRE IrDA USB OTG/ 2 Hosts ...

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... See supply voltage requirements. Part Order Number MC94MX21DVKN3 Freescale Semiconductor Table 4 on page 14 Table 1. Ordering Information Package Size Package Type 289-lead MAPBGA 0.65mm, 14mm x 14mm MC94MX21 Technical Data, Rev. 1.4 Introduction for core frequency and Operating Range ° ° Lead-free -30 C– ...

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... General-Purpose I/O (GPIO) Ports — Debug Capability 2 Signal Descriptions Table 2 identifies and describes the i.MX21 signals. Pin assignment is provided in Assignment and Package Information” and in the “Signal Multiplexing Scheme” table within the reference manual. 4 MC94MX21 Technical Data, Rev. 1 Section 4, “Pin Freescale Semiconductor ...

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... KΩ resistor to VDDA. Do not change the state of these inputs after power-up. Boot 3 should always be tied to logic low. Freescale Semiconductor depends solely upon the user application, however there are a few Table 2. i.MX21 Signal Descriptions Function/Notes External Bus/Chip Select (EIM) Bootstrap MC94MX21 Technical Data, Rev. 1.4 Signal Descriptions 5 ...

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... These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed functions, then configure as GPIO input with pull-up enabled, and leave connect. 6 Function/Notes SDRAM Controller Clocks and Resets MC94MX21 Technical Data, Rev. 1.4 Freescale Semiconductor ...

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... SLCDC1_RS. REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is multiplexed with SLCDC1_D0. Freescale Semiconductor Function/Notes JTAG CMOS Sensor Interface LCD Controller MC94MX21 Technical Data, Rev. 1.4 Signal Descriptions ® ® User Guide from ARM Limited. 7 ...

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... EXT_DMAREQ External DMA Request input signal. This signal is multiplexed with CSPI1_RDY. EXT_DMAGRANT External DMA Grant output signal. This signal is multiplexed with LD[16] of LCDC and CSPI1_SS1 of CSPI1. 8 Function/Notes Smart LCD Controller Bus Master Interface (BMI) External DMA MC94MX21 Technical Data, Rev. 1.4 Freescale Semiconductor ...

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... This signal is multiplexed with NFRE signal of NF. PC_PWRON PCMCIA input signal to indicate that the card power has been applied and stabilized. Freescale Semiconductor Function/Notes NAND Flash Controller PCMCIA Controller MC94MX21 Technical Data, Rev. 1.4 Signal Descriptions 9 ...

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... USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9. USBG_FS USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT signal of USB OTG. This signal is muxed with SLCDC1_DAT10. 10 Function/Notes CSPI General Purpose Timers USB On-The-Go MC94MX21 Technical Data, Rev. 1.4 Freescale Semiconductor ...

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... SD Data bidirectional signals. SD2_D[3:2] are multiplexed with SLCDC1_RS and SLCDC_D0 signals from SLCDC1. UART1_RXD Receive Data input signal UART1_TXD Transmit Data output signal UART1_RTS Request to Send input signal UART1_CTS Clear to Send output signal Freescale Semiconductor Function/Notes Secure Digital Interface UARTs – IrDA/Auto-Bauding MC94MX21 Technical Data, Rev. 1.4 Signal Descriptions 11 ...

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... SAP_FS Frame Sync signal which is output in master and input in slave. 2 I2C_CLK I C Clock 2 I2C_DATA I C Data OWIRE 1-Wire input and output signal. This signal is multiplexed with JTAG RTCK. 12 Function/Notes 2 S protocol and AC97 1-Wire MC94MX21 Technical Data, Rev. 1.4 Freescale Semiconductor ...

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... Quiet GND pins for silicon internal circuitry QVDDX Power supply pin for the ARM core. Externally connect directly to QVDD Freescale Semiconductor Function/Notes PWM General Purpose Input/Output Keypad Noisy Supply Pins Supply Pins – Analog Modules Internal Power Supplies MC94MX21 Technical Data, Rev. 1.4 Signal Descriptions 13 ...

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... Range” Table 3. Maximum Ratings Symbol QVDD QVDDX max, NVDD VDDA max, V Imax T storage Symbol DVKN T A NVDDx QVDD, QVDDx QVDD, QVDDx VDDA MC94MX21 Technical Data, Rev. 1.4 3) may cause (Table 4) is not implied. Min Max -0.3 2.1 max -0.3 3.3 max 1 -0.3 VDD + 0.3 -55 150 Table 4. Minimum Maximum ...

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... HYS NVDD NVDD I/O I/O = High impedance state Table 6. Input/Output Capacitance Symbol Min C i – – MC94MX21 Technical Data, Rev. 1.4 Specifications 1 Min Typ Max 0.7NVDD – NVDD O – 0.3NVDD 0.8NVDD – – – – 0.2NVDD – – ...

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... Table 9. CLKO Rise/Fall Time (at 30pF Loaded) Rise Time Fall Time 16 Table 7. Power Consumption Conditions min Table 8. 32k/26M Oscillator Signal Timing Best Case Typical Worst Case 0.80 1.00 1.40 0.74 1.08 1.67 MC94MX21 Technical Data, Rev. 1.4 Symbol Typ Max Units 180 QVDD QVDDX I 8 NVDD1 I through 6.6 NVDD2 NVDD6 VDDA ...

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... FPL mode and integer MF (does not include pre-multi lock-in time) – Integer MF, FPL mode, Vcc=1.7V FOL mode, integer MF 560 MHz, Vcc = 1.7V dck MC94MX21 Technical Data, Rev. 1.4 Specifications is a reference clock period after the Minimum Typical Maximum 16 – 320 16 – ...

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... RESET_POR RESET_DRAM HRESET RESET_OUT CLK32 HCLK RESET_IN HRESET RESET_OUT 6 CLK32 HCLK Figure 3. Timing Relationship with RESET_IN Exact 300ms Figure 2. Timing Relationship with POR 5 MC94MX21 Technical Data, Rev. 1.4 Figure 2 and 3 7 cycles @ CLK32 4 14 cycles @ CLK32 14 cycles @ CLK32 4 Freescale Semiconductor ...

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... Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External DMA request is de-asserted immediately after sensing grant signal active. Freescale Semiconductor Table 11. Reset Module Timing Parameters MC94MX21 Technical Data, Rev. 1.4 Specifications 1.8V ± 0.10V 3.0V ± 0.30V Min ...

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... MMD that data is ready in BMI TxFIFO for read access. MMD 20 t min_assert t max_req_assert t max_read 3.0 V WCS BCS 8 hclk + 8.6 8 hclk + 2.74 9 hclk - 20.66 9 hclk - 6.7 8 hclk - 6.21 8 hclk - 0.77 3 hclk - 15.87 3 hclk - 8.83 MC94MX21 Technical Data, Rev. 1.4 t max_write 1.8 V Unit WCS BCS 8 hclk + 7.17 8 hclk + 3. hclk - 17.96 9 hclk - 8. hclk - 5.84 8 hclk - 0. hclk - 15.9 3 hclk - 9.12 ns ...

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... MHz. Freescale Semiconductor 1T Tdh Tds TxD1 TxD2 Ts Symbol Minimum Typical 1T 33.3 – – Trh 6 – Tds 6 – Tdh 6 MC94MX21 Technical Data, Rev. 1.4 Specifications Trh Last TxD Maximum Unit – ns – ...

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... BMI_CLK/CS out once the BMI_WRITE is changed from low to high. 22 Can be asserted any time RxD1 RxD2 Tds Ts Table 14. MMD Write BMI Timing Symbol Minimum Tds 5 MC94MX21 Technical Data, Rev. 1.4 Can be asserted any time Last RxD Th Typical Maximum Unit – – ns – – ns – – ns ...

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... BMI_WRITE signal can not be negated when the WRITE operation is proceeding. Freescale Semiconductor 1T Tdh Tds TxD1 TxD2 Symbol Minimum Typical Tds 2 Tdh 2 Trh 2 MC94MX21 Technical Data, Rev. 1.4 Specifications Trh Last TxD Maximum Unit – – – ...

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... Each rising edge of BMI_CLK/CS will determine if data should be latched to RxFIFO from the data bus. 24 Total has COUNT+1 clocks in one burst Can be asserted any time Can be asserted any time RxD2 RxD1 Tds2 Tds1 Symbol Minimum Typical Tds1 14 – Tds2 14 – MC94MX21 Technical Data, Rev. 1.4 Last RxD Maximum Unit – ns – ns Freescale Semiconductor ...

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... Ttdh TxD RxD Read Write BMI BMI Symbol Minimum Typical Trdh 3 Ttds 6 Ttdh 6 Trh 6 MC94MX21 Technical Data, Rev. 1.4 Specifications Trh Last TxD Read BMI Maximum Unit – – ns – – ns – – ns – – – ...

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... WAIT signal. So the BMI_WRITE will be asserted at least for 1+WS Int_Clk period. 26 1+ws Last TxD TxD2 BMI write BMI write Figure 12 shows the BMI write timing when the WAIT bit is set. MC94MX21 Technical Data, Rev. 1.4 Figure 11 1+ws 1+ws RxD1 RxD2 Tdh written to READ bit of control reg1 Freescale Semiconductor ...

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... Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either CSPI1 or CSPI2. When the CSPI1 module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the external CSPI master’s timing. In this configuration, SS Freescale Semiconductor 1+ws 1+ws TXD_a 1+ws 1+ws RXD_a MC94MX21 Technical Data, Rev. 1.4 Specifications TXD_b RXD_b 27 ...

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... Figure 16. Master CSPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 17. Slave CSPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO Figure 18. Slave CSPI Timing Diagram FIFO Advanced by SS Rising Edge MC94MX21 Technical Data, Rev. 1.4 Freescale Semiconductor ...

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... Freescale Semiconductor Figure 14 Parameter Minimum 2T 3·Tsclk 2·Tsclk 0 Tsclk + WAIT Figure 19. SCLK to LD Timing Diagram Table 19. LCDC SCLK Timing Parameters Minimum MC94MX21 Technical Data, Rev. 1.4 Specifications through Figure 18 Maximum Unit 1 – – ns – ns – – ns – ...

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... XMAX is defined in number of pixels in one line. 30 Non-display region T3 T4 Line 1 T6 XMAX (0,1) (0,2) (0,X-1) Minimum T5+T6+T7-1 – Figure MC94MX21 Technical Data, Rev. 1.4 Display region Line Y T7 Value Unit (VWAIT1·T2)+T5+T6+T7-1 Ts XMAX+T5+T6+T7 Ts VWIDTH·T2 Ts (VWAIT2·T2)+1 Ts HWIDTH+1 Ts HWAIT2+3 Ts HWAIT1+1 Ts 20, all 3 signals are active low. ...

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... REV toggles in every HSYN period. Freescale Semiconductor XMAX Figure 21. Sharp TFT Panel Timing Table 21. Sharp TFT Panel Timing Minimum – MC94MX21 Technical Data, Rev. 1.4 Specifications D320 Value 1 HWAIT1+1 HWAIT2 + 4 CLS_RISE_DELAY+1 CLS_HI_WIDTH+1 PS_RISE_DELAY REV_TOGGLE_DELAY+1 Unit Ts ...

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... When monochrome mode with bus width = 2, 4, and and 4 Tpix respectively XMAX Figure 22. Non-TFT Mode Panel Timing Table 22. Non-TFT Mode Panel Timing Minimum 2 1 – 1 MC94MX21 Technical Data, Rev. 1 Value HWAIT2+2 HWIDTH+1 ≤ ≤ ...

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... SCKPOL = 0, CSPOL = MSB T6 RS=0 ≥ command data, RS=1≥ display data SCKPOL = 1, CSPOL = MSB T6 RS=0 ≥ command data, RS=1≥ display data SCKPOL = 0, CSPOL = 1 Figure 23. SLCDC Serial Transfer Timing MC94MX21 Technical Data, Rev. 1.4 Specifications LSB LSB LSB T3 T5 ...

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... T2 T3 command data CSPOL = command data CSPOL = 1 Figure 24. SLCDC Parallel Transfers Timing Table 24. SLCDC Parallel Transfers Timing Minimum MC94MX21 Technical Data, Rev. 1.4 Maximum Unit 962 ns – ns – ns – ns – ns – ns – ns display data display data Maximum ...

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... Freescale Semiconductor Valid Data 7 Valid Data 6a Table 25. SDHC Bus Timing Parameters 1.8 V ± 0.1 V Min 1 —10/30 cards 6/33 15/75 – – 5.7/5.7 5.7/5.7 5.7/5.7 5.7/5.7 0 MC94MX21 Technical Data, Rev. 1.4 Specifications Valid Data Valid Data 6b 3.0 V ± 0.3 V Max Min Max 25/5 0 25/5 400 0 400 – 10/50 – – 10/50 – 3 10/50 (5.00) – ...

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... ID Host Command Content CRC ****** N cycles CR Host Command Content CRC ****** MC94MX21 Technical Data, Rev. 1.4 Figure 26 through through Figure 30 Host Active Definition Start bit (0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (1) End bit (1) CID/OCR Content Identification Timing CID/OCR ...

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... Timing response end to next CMD start (data transfer mode) N cycles CRC ****** Timing of command sequences (all modes) until the card sees a stop transmission command. The AC MC94MX21 Technical Data, Rev. 1.4 Specifications Response CRC Content Host Command CRC Content Host Command ...

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... CRC ****** ***** Timing of stop command Valid Read Data (CMD12, data transfer mode) Figure 28. Timing Diagrams at Data Read MC94MX21 Technical Data, Rev. 1.4 Response CRC E Z Content ***** Read Data ***** ***** Read Data N cycles AC Timing of multiple block read ...

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... The stop transmission command may occur when the card is in different states. different scenarios on the bus. Freescale Semiconductor Figure 29. Timing Diagrams at Data Write MC94MX21 Technical Data, Rev. 1.4 Specifications Figure 30 shows the 39 ...

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... MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle 40 Figure 26 through Symbol Minimum NCR 2 NID 5 NAC 2 MC94MX21 Technical Data, Rev. 1.4 Figure 30 Maximum Unit 64 Clock cycles 5 Clock cycles TAAC + NSAC Clock cycles Freescale Semiconductor ...

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... Figure 31. SDIO IRQ Timing Diagram CMD52 CRC Figure 32. SDIO ReadWait Timing Diagram MC94MX21 Technical Data, Rev. 1.4 Specifications Figure 30 (Continued) Maximum – Clock cycles – Clock cycles – ...

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... NFALE NFIO[7:0] Figure 33. Command Latch Cycle Timing DIagram 42 Figure 36 depict the relative timing requirements among different Table 28 lists the timing parameters. The NAND Flash Controller NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 command MC94MX21 Technical Data, Rev. 1.4 Freescale Semiconductor ...

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... Time it takes for SW to issue the next address command NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to Flash Figure 35. Write Data Latch Timing DIagram NF14 NF3 NF13 NF16 Data from Flash NF12 Figure 36. Read Data Latch Timing Diagram MC94MX21 Technical Data, Rev. 1.4 Specifications Address NF4 NF15 NF17 43 ...

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... T – tRR 4T – 180 tRP 1.5T – 67.5 tRC 2T – tREH 0.5T – 22.5 tDSR 15 – tDHR 0 – MC94MX21 Technical Data, Rev. 1 NFC Clock NFC Clock 22.17 MHz 33.25 MHz Max Min Max 45 – 30 – 45 – 30 – 45 – 30 – 45 – ...

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... Freescale Semiconductor Figure 37. PWM Output Timing Diagram Table 29. PWM Output Timing Parameters 1.8 V ± 0.1 V Minimum Maximum 12.29 – 9.91 – – 0.5 – 0.5 9.37 – 8.71 – MC94MX21 Technical Data, Rev. 1.4 Specifications 3.0 V ± 0.3 V Unit Minimum Maximum 0 45 MHz 12.29 – 9.91 – – 0.5 – 0.5 3.61 – 3.03 – ...

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... COL/ Data Note: CKE is high during the read/write cycle. 1.8 V ± 0.1 V Minimum 3.00 3.00 7.5 4.78 3.03 MC94MX21 Technical Data, Rev. 1.4 2 3.0 V ± 0.3 V Maximum Minimum Maximum – 3 – – 3 – – 7.5 – – 3 – – 2 – Freescale Semiconductor Unit ...

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... Freescale Semiconductor 1.8 V ± 0.1 V Minimum 3.67 2.95 – – – 2 – – – RCD setting can be found in the i.MX21 reference manual. RCD ROW/BA 8 MC94MX21 Technical Data, Rev. 1.4 Specifications 3.0 V ± 0.3 V Maximum Minimum Maximum – 2 – – 2 – – 5.4 5.4 – 6.0 6.0 – – – – ...

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... CAS ADDR BA DQ DQM 48 1.8 V ± 0.1 V Minimum Maximum 3.00 3.00 7.5 3.67 2. RCD 3.41 2. Figure 40. SDRAM Refresh Timing Diagram MC94MX21 Technical Data, Rev. 1.4 3.0 V ± 0.3 V Minimum Maximum – 3 – – 3 – – 7.5 – – 2 – – 2 – 2 – t – – t – RCD – ...

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... DQM CKE Figure 41. SDRAM Self-Refresh Cycle Timing Diagram Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 3.00 – 3.00 – 7.5 – 3.67 – 2.95 – – – RC MC94MX21 Technical Data, Rev. 1.4 Specifications 3.0 V ± 0.3 V Unit Minimum Maximum 3 – – ns 7.5 – – – – ns ...

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... The SSI can be connected to 4 set of ports, SAP, SSI1, SSI2 and SSI3. CK Output FS (bl) Output FS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 42. SSI Transmitter Internal Clock Timing Diagram 50 Figure 45 MC94MX21 Technical Data, Rev. 1 Freescale Semiconductor ...

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... Figure 44. SSI Transmitter External Clock Timing Diagram CK Input FS (bl) Input FS (wl) Input SRXD Input Figure 45. SSI Receiver External Clock Timing Diagram Freescale Semiconductor MC94MX21 Technical Data, Rev. 1.4 Specifications ...

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... CK high to STXD high impedance 29 SRXD setup time before (Rx) CK low 30 SRXD hole time after (Rx) CK low 52 1.8 V ± 0.1 V Minimum Maximum 1 Internal Clock Operation (SAP Ports) 90.91 -3.30 -3.93 -3.30 -3.93 -3.30 -3.93 -3.30 -3.93 -2.44 -2.44 -2.44 -2.67 23.68 0 External Clock Operation (SAP Ports) 90.91 36.36 36.36 10.24 10.89 10.24 10.89 10.24 10.89 10.24 10.89 12.08 10.80 10.80 12.08 0.37 0 MC94MX21 Technical Data, Rev. 1.4 3.0 V ± 0.3 V Minimum Maximum – 90.91 – -1.16 -2.98 -1.10 -1.34 -4.18 -1.43 -1.16 -2.98 -1.10 -1.34 -4.18 -1.43 -1.16 -2.98 -1.10 -1.34 -4.18 -1.43 -1.16 -2.98 -1.10 -1.34 -4.18 -1.43 -0.60 -2.65 -0.98 -0.60 -2.65 -0.98 -0.60 -2.65 -0.98 -0.99 -2.65 -0.98 – 22.09 – ...

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... CK high to FS (bl) high Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 23.00 0 1.20 0 1.8 V ± 0.1 V Minimum Maximum 1 (SSI1 Ports) Internal Clock Operation 90.91 -0.68 -0.96 -0.68 -0.96 -0.68 -0.96 -0.68 -0.96 -1.68 -1.68 -1.68 -1.58 20.41 0 External Clock Operation (SSI1 Ports) 90.91 36.36 36.36 10.22 10.79 MC94MX21 Technical Data, Rev. 1.4 Specifications 3.0 V ± 0.3 V Minimum Maximum – 21.41 – – 0 – – 0.88 – – 0 – 3.0 V ± 0.3 V Minimum Maximum – 90.91 – -0.15 -0.68 -0.15 -0.27 -0.96 -0.27 -0.15 -0.68 -0.15 -0.27 -0.96 -0.27 -0.15 -0 ...

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... CK high to FS (wl) low 9 (Rx) CK high to FS (wl) low 10 (Tx) CK high to STXD valid from high impedance 54 1.8 V ± 0.1 V Minimum Maximum 10.22 10.79 10.22 10.79 10.22 10.79 10.05 10.00 10.00 10.05 0.78 0 19.90 0 2.59 0 1.8 V ± 0.1 V Minimum Maximum 1 Internal Clock Operation (SSI2 Ports) 90.91 0.01 -0.21 0.01 -0.21 0.01 -0.21 0.01 -0.21 0.34 MC94MX21 Technical Data, Rev. 1.4 3.0 V ± 0.3 V Minimum Maximum 17.63 8.82 16.24 19.67 9.39 18.28 17.63 8.82 16.24 19.67 9.39 18.28 17.63 8.82 16.24 19.67 9.39 18.28 15.75 8.66 14.36 15.63 8.61 14.24 15.63 8.61 14.24 15.75 8.66 14.36 – 0.47 – – 0 – – ...

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... STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 0.34 0.34 0.34 21.50 0 External Clock Operation (SSI2 Ports) 90.91 36.36 36.36 10.40 11.00 10.40 11.00 10.40 11.00 10.40 11.00 9.59 9.59 9.59 9.59 2.52 0 20.78 0 4.42 0 MC94MX21 Technical Data, Rev. 1.4 Specifications 3.0 V ± 0.3 V Minimum Maximum 0.72 0.34 0.72 0.72 0.34 0.72 0.48 0.34 0.48 – 21.50 – – 0 – – 90.91 – – 36.36 – – 36.36 – 17.37 8.67 15.88 19 ...

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... CK high to STXD valid from high impedance 27a (Tx) CK high to STXD high 27b (Tx) CK high to STXD low 56 1.8 V ± 0.1 V Minimum Maximum 1 Internal Clock Operation (SSI3 Ports) 90.91 -2.09 -2.74 -2.09 -2.74 -2.09 -2.74 -2.09 -2.74 -1.73 -2.87 -2.87 -1.73 22.77 0 External Clock Operation (SSI3 Ports) 90.91 36.36 36.36 9.62 10.30 9.62 10.30 9.62 10.30 9.62 10.30 9.02 8.48 8.48 MC94MX21 Technical Data, Rev. 1.4 3.0 V ± 0.3 V Minimum Maximum – 90.91 – -0.66 -2.09 -0.66 -0.84 -2.74 -0.84 -0.66 -2.09 -0.66 -0.84 -2.74 -0.84 -0.66 -2.09 -0.66 -0.84 -2.74 -0.84 -0.66 -2.09 -0.66 -0.84 -2.74 -0.84 -0.26 -1.73 -0.26 -0.80 -2.87 -0.80 -0.80 -2.87 -0.80 -0.26 -1.73 -0.26 – ...

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... The one-wire will sample for the DS2502 presence pulse. The presence pulse is latched in the one-wire Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 9.02 16.46 1.49 0 21.99 0 3.80 0 Figure 46. DS2502 waits DS2502 Tx 15-60us “presence pulse” 60-240us 68us Figure 46. 1-Wire Initialization MC94MX21 Technical Data, Rev. 1.4 Specifications 3.0 V ± 0.3 V Minimum Maximum 7.29 14.97 – 1.49 – – 0 – – 21.99 – – 0 – – 3.80 – – ...

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... After a Read, the control register RDST bit is set to the value of the read. 58 AutoClear WR0 Set WR0 Write 0 Slot 128us 17us 100us Figure 47. Write 0 Timing Auto Clear WR1/R Set WR1/RD Write “1” Slot 117us 5us Figure 48. Write 1 Timing MC94MX21 Technical Data, Rev. 1.4 Freescale Semiconductor ...

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... Table 38. System Clock Requirements NOTE: MC94MX21 Technical Data, Rev. 1.4 Specifications Auto Clear WR1/R Read “1” Slot 117us One-Wire samples (set RDST) 13us Absolute Relative Precision Precision 31 0.0645 7 0.1 32 0.0645 20 0 ...

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... USBD_TXDP high to USBD_OE deactivated TXDP_ OEB USBD_TXDM low to USBD_OE deactivated (includes SE0) TXDM_ OEB SE0 interval of EOP FEOPT Data transfer rate PERIOD PERIOD 2 Parameter MC94MX21 Technical Data, Rev. 1 TXDM_OEB 3 t TXDP_OEB t FEOPT 5 3.0 V ± 0.3 V Unit Minimum Maximum 83.14 83.47 ns 81.55 81.98 ns 83.54 83.8 ns 248 ...

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... Data hold time 3 Data setup time 4 HIGH period of the SCL clock 5 LOW period of the SCL clock 6 Setup time for STOP condition Freescale Semiconductor Parameter Parameter MC94MX21 Technical Data, Rev. 1.4 Specifications 1 t FEOPR 3.0 V ± 0.3 V Minimum Maximum 82 – 1.8 V ± ...

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... Burst Clock (falling edge) Read Data Write Data (negated falling) Write Data (negated rising) DTACK 10a Figure 53. EIM Bus Timing Diagram MC94MX21 Technical Data, Rev. 1 10a Freescale Semiconductor ...

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... Burst Clock (BCLK) cycle time 1. Clock refers to the system clock signal, HCLK, generated from the System DPLL Freescale Semiconductor Table 42. EIM Bus Timing Parameters 1.8 V ± 0.1 V Min Typical 3.97 6.02 3.93 6.00 3.47 5.59 3.39 5.09 3.51 5.56 3.59 5.37 3.62 5.49 3.70 5.61 3.60 5.48 3.69 5.62 3.69 5.46 4.64 5.47 3.52 5.06 3.50 5.05 3.65 5.28 3.65 5.67 3.66 5.69 3.50 5.22 3.49 5.19 3.50 5.22 3.49 5.19 4.54 – 0.5 – 4.13 5.86 4.10 5.79 4.02 5.81 2.65 4.63 15 – MC94MX21 Technical Data, Rev. 1.4 Specifications 1.8 V ± 3.0 V ± 0.3 V 0.1 V Max Min Typical Max 9.89 3.83 5.89 9.79 9.86 3.81 5.86 9.76 8.62 3.30 5.09 8.45 8.27 3.15 4.85 8.03 8.79 3.39 5.39 8.51 9.14 3.36 5.20 8.50 8.98 3.46 5.33 9.02 9.26 3.46 5.37 8.81 8.77 3.44 5.30 8.88 9.12 3.42 5.36 8.60 8.71 3.46 5.25 8.54 8.70 3.46 5.25 8.54 8.39 3.41 5.18 8.36 8.27 3.41 5 ...

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... Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Address CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN 64 Seq/Nonseq Read V1 Last Valid Data Read Figure 54. WSC = 1, A.HALF/E.HALF MC94MX21 Technical Data, Rev. 1 Freescale Semiconductor ...

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... Write haddr hready hwdata Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Address CS[0] R/W LBA OE EB D[31:0] Figure 55. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF Freescale Semiconductor V1 Write Data (V1) Last Valid Data Last Valid Data MC94MX21 Technical Data, Rev. 1.4 Specifications Unknown V1 Write Write Data (V1) 65 ...

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... Nonseq hwrite Read haddr V1 hready weim_hrdata Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 56. WSC = 1, OEA = 1, A.WORD/E.HALF 66 Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

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... V1 hready hwdata Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[0] R/W LBA OE EB D[31:0] Figure 57. WSC = 1, WEA = 1, WEN = 1, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 Specifications Address Write 2/2 Half Word 67 ...

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... Nonseq htrans hwrite Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 58. WSC = 3, OEA = 2, A.WORD/E.HALF 68 Last Valid Data Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB D[31:0] Last Valid Data Figure 59. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 Specifications Address 2/2 Half Word 69 ...

Page 70

... Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 60. WSC = 3, OEA = 4, A.WORD/E.HALF 70 Last Valid Data Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

Page 71

... Last Valid hwdata Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 61. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 Specifications Address 2/2 Half Word 71 ...

Page 72

... Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 62. WSC = 3, OEN = 2, A.WORD/E.HALF 72 Last Valid Data Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

Page 73

... Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready BCLK Last Valid Addr A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 63. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 Specifications V1 Word Address 2/2 Half Word 73 ...

Page 74

... Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 64. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 74 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 Unknown Address 2/2 Half Word Freescale Semiconductor ...

Page 75

... Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 65. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC94MX21 Technical Data, Rev. 1.4 Specifications Unknown Address 2/2 Half Word 75 ...

Page 76

... Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 66. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF 76 Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC94MX21 Technical Data, Rev. 1.4 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

Page 77

... EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 67. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF Freescale Semiconductor Read Idle Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC94MX21 Technical Data, Rev. 1.4 Specifications Write Write Data Read Data Address V8 Write Write Data 77 ...

Page 78

... BCLK A[24:0] Last Valid Addr CS[3:0] R/W LBA OE EB D[31:0] Last Valid Data Figure 68. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF 78 Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC94MX21 Technical Data, Rev. 1.4 Address Write Data (2/2 Half Word) Freescale Semiconductor ...

Page 79

... Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 69. WSC = 3, CSA = 1, A.HALF/E.HALF Freescale Semiconductor Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC94MX21 Technical Data, Rev. 1.4 Specifications Write Data Read Data Address V8 Write Write Data 79 ...

Page 80

... Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 70. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF 80 Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC94MX21 Technical Data, Rev. 1.4 Read Data (V2) Address V2 Read Data (V2) Freescale Semiconductor ...

Page 81

... OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 71. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF Freescale Semiconductor Idle Nonseq Write V8 Last Valid Data Address V1 CNC Read Read Data Last Valid Data MC94MX21 Technical Data, Rev. 1.4 Specifications Write Data Read Data Address V8 Write Write Data 81 ...

Page 82

... Nonseq hwrite Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 72. WSC = 3, SYNC = 1, A.HALF/E.HALF 82 Nonseq Read V5 Address V1 Read V1 Word V2 Word MC94MX21 Technical Data, Rev. 1.4 Idle Address V5 V5 Word V6 Word Freescale Semiconductor ...

Page 83

... Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 73. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD Freescale Semiconductor Seq Seq Read Read Word V2 Word Address V1 Read V1 Word V2 Word MC94MX21 Technical Data, Rev. 1.4 Specifications Idle Seq Read V4 V3 Word V4 Word V3 Word V4 Word 83 ...

Page 84

... Read haddr V1 hready weim_hrdata Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 74. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF 84 Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC94MX21 Technical Data, Rev. 1.4 Idle V2 Word Address V2 V2 1/2 V2 2/2 Freescale Semiconductor ...

Page 85

... BCLK Last Valid A[24:0] Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 75. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read V1 1/2 MC94MX21 Technical Data, Rev. 1.4 Specifications Idle Seq Read V2 V1 Word V2 Word V1 2/2 V2 1/2 V2 2/2 85 ...

Page 86

... V1 hready weim_hrdata weim_hready BCLK Last Valid A[24:0] Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 76. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF 86 Last Valid Data Address V1 Read V1 1/2 MC94MX21 Technical Data, Rev. 1.4 Idle Seq Read V2 V1 Word V2 Word V1 2/2 V2 1/2 V2 2/2 Freescale Semiconductor ...

Page 87

... Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The waveforms in the following section provide examples of the DTACK signal operation. Freescale Semiconductor Specifications” for more information on how to generate MC94MX21 Technical Data, Rev. 1.4 Specifications 87 ...

Page 88

... DTACK Example Waveforms: Internal ARM AHB Word Accesses to Word-Width (32-bit) Memory HCLK BCLK Last Valid ADDR Addr CS[5] RW LBA OE EB (EBC=0) EB (EBC=1) DTACK DATA_IN Figure 77. DTACK Edge Triggered Read Access, WSC=3F, OEA=8, OEN=5, AGE= Read MC94MX21 Technical Data, Rev. 1.4 V1 Data Freescale Semiconductor ...

Page 89

... HCLK BCLK ADDR Last Valid Addr CS[0] RW LBA OE EB (EBC=0) EB (EBC=1) DTACK DATA_IN Figure 78. DTACK Level Sensitive Sequential Read Accesses, WSC=2, EW=1, DCT=1, AGE=0 (Example of Freescale Semiconductor Address V1 Read DCT V1 Word DTACK Remaining High) MC94MX21 Technical Data, Rev. 1.4 Specifications V1+8 V1+4 V1+4 Word V1+8 Word 89 ...

Page 90

... Specifications HCLK BCLK ADDR Last Valid Addr CS[0] RW LBA OE EB DTACK DATA_OUT Figure 79. DTACK Level Sensitive Sequential Write Accesses, WSC=2, EW=1, RWA=1, RWN=1, DCT=1, 90 Address V1 RWA RWN Write DCT V1 Word AGE=0 (Example of DTACK Asserting) MC94MX21 Technical Data, Rev. 1.4 V1+4 V1+8 V1+4 Word V1+8 Freescale Semiconductor ...

Page 91

... Figure 80. Definition of Bus Timing for I 2 Table 43 Bus Timing Parameters 1.8 V ± 0.1 V Minimum Maximum 0 114.8 0 3.1 69.7 336.4 110.5 Section 3.22.3, “Calculation of Pixel Clock Rise/ MC94MX21 Technical Data, Rev. 1.4 Specifications 3.0 V ± 0.3 V Minimum Maximum 100 0 100 – 111.1 – 69.7 0 72.3 – 1.76 – ...

Page 92

... Valid Data Valid Data Valid Data 3 4 Parameter Minimum HCLK HCLK T HCLK 0 = Period for HCLK Period of CSI_PIXCLK P MC94MX21 Technical Data, Rev. 1 Valid Data Valid Data Maximum Unit – / – ns – ns – ns – ...

Page 93

... Figure 83. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge Freescale Semiconductor Figure 84 Section 3.22.3, “Calculation of Pixel Clock Rise/ 1 Valid Data Valid Data 2 3 MC94MX21 Technical Data, Rev. 1.4 Specifications shows the timing diagram Table 45. The formula for Valid Data 93 ...

Page 94

... Valid Data Valid Data 2 3 Parameter Minimum HCLK HCLK T HCLK 0 = Period of HCLK HCLK MC94MX21 Technical Data, Rev. 1 Valid Data 1 Maximum Unit – ns – ns – ns – ns – ns HCLK / 2 MHz ...

Page 95

Pin Assignment and Package Information OE_ A LD9 LD12 LD14 REV HSYNC SD2_D2 ACD CON B LD7 LD5 LD11 LD16 PS SD2_D0 TRAST C LD1 LD3 LD6 LD10 LD17 VSYNC SD2_D3 D LD2 ...

Page 96

... Pin Assignment and Package Information 4.1 MAPBGA Package Dimensions Figure 85 illustrates the MAPBGA 14 mm × × 1.41 mm package, which has 0.65 mm ball pitch. Figure 85. i.MX21 MAPBGA Mechanical Drawing 96 MC94MX21 Technical Data, Rev. 1.4 Freescale Semiconductor ...

Page 97

... Document Revision History Rev 1.4 is the initial public release of this document. Freescale Semiconductor MC94MX21 Technical Data, Rev. 1.4 Document Revision History 97 ...

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... P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MC94MX21 Rev. 1.4 08/2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...