mc94mx21 Freescale Semiconductor, Inc, mc94mx21 Datasheet - Page 26

• Manufacturer Part Number: mc94mx21
• Description: 333 And 350 Mhz
• Manufacturer: Freescale Semiconductor, Inc

Specifications
3.8.3.1
The WAIT control bit (BMICTLR1[29]) is used in this mode. When this bit is cleared (default), the
BMI_WAIT signal is ignored and the CS cycle is terminated by Wait State (WS) control bits.
shows the BMI timing when the WAIT bit is cleared.
3.8.3.2
When the WAIT control bit is set, the BMI_WAIT signal is used and the CS cycle is terminated upon
sampling a logic high BMI_WAIT signal.
When the BMI_WRITE is asserted, the BMI will detect the BMI_WAIT signal on every falling edge of
the Int_Clk. When it detected the high level of the BMI_WAIT, the BMI_WRITE will be negated after
1+WS Int_Clk period. If the BMI_WAIT is always high or already high before BMI_WRITE is asserted,
this timing will same as without WAIT signal. So the BMI_WRITE will be asserted at least for 1+WS
Int_Clk period.
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Figure 11. Memory Interface Master Mode, BMI Read/Write to External Slave Device Timing without Wait
BMI_READ_REQ
(reference only)
(reference only)
BMI_CLK/CS
BMI_D[15:0]
BMI_WRITE
BMI_READ
Int_write
Int_Clk
Memory Interface Master Mode Without WAIT Signal
Memory Interface Master Mode with WAIT Signal
DMA or CPU write data to TxFIFO
On the next Int_Clk BMI issues a write cycle
Signal (MMD_MODE_SEL=0, MASTER_MODE_SEL=1)
BMI_READ_REQ is still logic high, BMI issues next write cycle
1+ws
TxD1
BMI write
1+ws
MC94MX21 Technical Data, Rev. 1.4
BMI write
TxD2
Figure 12
Last TxD
BMI write
shows the BMI write timing when the WAIT bit is set.
A 1 is written to READ bit of control reg1
1+ws
RxD1
1+ws
Tdh
Freescale Semiconductor
RxD2
Figure 11