mc94mx21 Freescale Semiconductor, Inc, mc94mx21 Datasheet - Page 5

• Manufacturer Part Number: mc94mx21
• Description: 333 And 350 Mhz
• Manufacturer: Freescale Semiconductor, Inc

The connections of the pins in
factory test signals that are not used in a normal application. Following is a list of these signals and how
they are to be terminated for proper operation of the i.MX21 processor:
Freescale Semiconductor
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Signal Name
BOOT [3:0]
CS [5:0]
D [31:0]
A [25:0]
DTACK
BCLK
CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.
OSC26M_TEST: To ensure proper operation, leave this signal as no connect.
EXT_48M: To ensure proper operation, connect this signal to ground.
EXT_266M: To ensure proper operation, connect this signal to ground.
TEST_WB[2:0]: These signals are also multiplexed with GPIO PORT E as well as alternate
keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed
function, then configure as GPIO input with pull up enabled, and leave as a no connect.
TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects.
ECB
EB0
EB1
EB2
EB3
LBA
RW
OE
Address bus signals
Data bus signals
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24], shared with SDRAM
DQM0.
Byte Strobe—Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1.
Byte Strobe—Active low external enable byte signal that controls D [15:8], shared with SDRAM DQM2
and PCMCIA PC_REG.
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0], shared with SDRAM
DQM3 and PCMCIA PC_IORD.
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR.
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is
selected. DTACK is multiplexed with CS4.
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-
going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also
shared with the PCMCIA PC_WE.
DTACK signal—External input data acknowledge signal, multiplexed with CS4.
System Boot Mode Select—The operational system boot mode upon system reset is determined by the
settings of these pins. To hardwire these inputs low, terminate with a 1 KΩ resister to ground. For a logic
high, terminate with a 1 KΩ resistor to VDDA. Do not change the state of these inputs after power-up.
Boot 3 should always be tied to logic low.
Table 2
Table 2. i.MX21 Signal Descriptions
MC94MX21 Technical Data, Rev. 1.4
depends solely upon the user application, however there are a few
External Bus/Chip Select (EIM)
Bootstrap
Function/Notes
Signal Descriptions
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