78p2343jat Teridian Semiconductor Corporation, 78p2343jat Datasheet - Page 12

• Manufacturer Part Number: 78p2343jat
• Description: 3-port E3/ds3/sts-1 With Jitter Attenuator
• Manufacturer: Teridian Semiconductor Corporation

78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION
ADDRESS N-3: JITTER ATTENUATOR CONTROL REGISTER
Page 12 of 37
BIT
3:2
7
6
5
4
1
0
NAME
RSVD
RSVD
JABW
JAEN
JASL
JLBK
ESP
[1:0]
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VALUE
DFLT
11
X
X
X
0
0
0
(continued)

2005 Teridian Semiconductor Corporation
Jitter Attenuator Enable:
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
Jitter Attenuation Selection:
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
Jitter Attenuator Local Loopback Enable:
NOTE: If both RLBK and JLBK bits are set, RLBK mode takes priority.
Reserved. Must be set to zero.
FIFO Elastic Store Pointer Selection:
Reserved. Must be set to zero.
Jitter Attenuator Bandwidth Selection:
(see JAT Bandwidth Selection Table on page 5)
NOTE: The default values of these register bits depend on the state of
the MSL0 pin upon power-up or reset. If the state of the MSL0 pin
selects E3 or DS3 mode, the default value of JABW is ‘0’. If the state of
the MSL0 pin selects STS1 mode, the default value of JABW is ‘1’.
0 : Disables jitter attenuation function
1 : Enables jitter attenuation function
0 : Jitter Attenuator on the receive path
1 : Jitter Attenuator on the transmit path
0 : Normal Operation
1 : TCLKx, TPOSx, TNEGx connected to JAT input and
ESP[1:0] = 00 : Pass-through
0 : Low bandwidth
1 : High bandwidth
RCLKx, RPOSx, RNEGx connected to JAT output
01 :
10 : 16 UI
11 : 32 UI (default)
8 UI
DESCRIPTION
Rev 2.2