xr16v598 Exar Corporation, xr16v598 Datasheet - Page 11

• Manufacturer Part Number: xr16v598
• Description: 2.25v To 3.6v High Performance Octal Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X or 8X or 4X (if
8X or 4X sampling is selected via the
(or 8 or 4) clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the
proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line
Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
F
2.7
2.7.1
2.7.2
IGURE
Output Data
Required
1000000
400000
460800
500000
750000
921600
Rate
5. T
Transmitter
T
ABLE
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
RANSMITTER
4: T
D
IVISOR FOR
YPICAL DATA RATES WITH A
(Decimal)
3.2552
1.6276
Clock
16X or 8X or 4X Clock
3.75
1.5
3
2
O
PERATION IN NON
16x
Data
Byte
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
O
BTAINABLE IN
D
3 12/16
1 10/16
3 4/16
1 8/16
8XMODE Register
Transmit Shift Register (TSR)
IVISOR
598
3
2
-FIFO M
Transmit
Register
Holding
24 MH
(THR)
DLM P
V
ODE
ALUE
Z CRYSTAL OR EXTERNAL CLOCK AT
11
ROGRAM
0
0
0
0
0
0
(HEX)
or 4XMODE Register) internal clock. A bit time is 16
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
DLL P
V
ALUE
M
S
B
3
3
3
2
1
1
ROGRAM
(HEX)
L
S
B
TXNOFIFO1
DLD P
V
ALUE
16X S
C
ROGRAM
A
4
0
0
8
(HEX))
AMPLING
XR16V598
D
ATA
R
ATE
0.16
0.16
0
0
0
0
E
RROR
(%)