xr16v598 Exar Corporation, xr16v598 Datasheet - Page 24

• Manufacturer Part Number: xr16v598
• Description: 2.25v To 3.6v High Performance Octal Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

XR16V598
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
The XR16V598 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1,
INT2 and INT3]. The four registers are in the device configuration register address space.
All four registers default to logic zero (as indicated in square braces) for no interrupt pending. All 8 channel
interrupts are enabled or disabled in each channel’s IER register. INT0 shows individual status for each
channel while INT1, INT2 and INT3 show the details of the source of each channel’s interrupt with its unique 3-
bit encoding.
wake-up interrupts are masked in the device configuration registers,
generated (if enabled) by the 598 when awakened from sleep if all 8 channels were placed in the sleep mode
previously.
A
3.1.1
[A7:A0]
DDRESS
0x8A
0x8B
0x8C
0x8D
0x8E
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
W
R
The Global Interrupt Source Registers
R/W
R/W TIMER LSB
R/W
R/W
R/W
R/W
R/W
EAD
W
RITE
R
R
R
R
R
R
R
Figure 13
/
INT Source
8X MODE
4X MODE
R
RESET
TIMER
TIMER
TIMER
SLEEP
REGB
EGISTER
DREV
CTRL
INT 1
INT 2
INT 3
DVID
MSB
shows the 4 interrupt registers in sequence for clarity. The 16-bit timer and sleep
UART 7
UART 2
UART 5
UART 7
UART 7
UART 7
UART 7
UART 7
Enable
Reset
sleep
Bit 7
bit 1
bit 0
bit 2
bit 7
bit 7
bit 7
[0x00]
T
INT3
0
0
0
0
ABLE
8: D
interrupt
UART 6
UART 4
UART 6
UART 6
UART 6
UART 6
Enable
source
Reset
sleep
Bit 6
bit 0
bit 2
bit 1
bit 6
bit 6
bit 6
0
0
1
0
EVICE
[0x00]
INT2
C
interrupt
UART 5
UART 1
UART 5
UART 5
UART 5
UART 5
source
Enable
Reset
ONFIGURATION
sleep
Bit 5
bit 2
bit 1
bit 0
bit 5
bit 5
bit 5
0
0
0
0
24
[0x00]
INT1
interrupt
UART 4
UART 6
UART 4
UART 4
UART 4
UART 4
Enable
source
Reset
sleep
Bit 4
bit 1
bit 0
bit 2
bit 4
bit 4
bit 4
0
0
1
0
R
EGISTERS
TimerCtrl
interrupt
UART 3
UART 3
UART 3
UART 3
UART 3
UART 3
TIMERCNTL and SLEEP.
Enable
source
Reset
sleep
[0x00]
Bit 3
bit 0
bit 2
bit 1
bit-3
bit 3
bit 3
bit 3
INT0
0
1
0
TimerCtrl
interrupt
UART 2
UART 0
UART 2
UART 2
UART 2
UART 2
Enable
source
Reset
sleep
Bit 2
bit-2
bit 2
bit 1
bit 0
bit 2
bit 2
bit 2
0
0
0
TimerCtrl
interrupt
UART 1
UART 5
UART 1
UART 1
UART 1
UART 1
Enable
source
Reset
sleep
Bit 1
bit 1
bit 0
bit 2
bit-1
bit 1
bit 1
bit 1
0
0
0
An interrupt is
REV. 1.0.2
write to all
TimerCtrl
UART 0
UART 2
UART 0
UART 0
UART 0
UART 0
Enable
UARTs
source
source
Reset
sleep
Bit 0
bit 0
bit 2
bit 1
bit-0
bit 0
bit 0
bit 0
0
0