sc16c554dbib64 NXP Semiconductors, sc16c554dbib64 Datasheet - Page 11

• Manufacturer Part Number: sc16c554dbib64
• Description: 5 V, 3.3 V And 2.5 V Quad Uart, 5 Mbit/s Max. With 16-byte Fifos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 2:
SC16C554B_554DB_3
Product data sheet
Symbol
CTSA
CTSB
CTSC
CTSD
D0 to D2,
D3 to D7
DSRA
DSRB
DSRC
DSRD
DTRA
DTRB
DTRC
DTRD
GND
INTA
INTB
INTC
INTD
Pin description
Pin
PLCC68 LQFP64 LQFP80 HVQFN48
11
25
45
59
66 to 68,
1 to 5
10
26
44
60
12
24
46
58
6, 23,
40, 57
15
21
49
55
2
16
33
47
53 to 55,
56 to 60
1
17
32
48
3
15
34
46
14, 28,
45, 61
6
12
37
43
…continued
23
38
63
78
7 to 9,
11 to 15
22
39
62
79
24
37
64
77
16, 36,
56, 76
27
34
67
74
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
1
12
26
-
39 to 41,
42 to 46
-
-
25
-
-
-
27
-
21, 37, 47 I
4
10
30
36
Rev. 03 — 1 September 2005
Type
I
I/O
I
O
O
Description
Clear to Send (active LOW). These inputs are
associated with individual UART channels A to D. A
logic 0 on the CTS pin indicates the modem or data set
is ready to accept transmit data from the
SC16C554B/554DB. Status can be tested by reading
MSR[4]. This pin only affects the transmit or receive
operations when auto-CTS function is enabled via
MCR[5] for hardware flow control operation.
Data bus (bidirectional). These pins are the 8-bit,
3-state data bus for transferring information to or from
the controlling CPU. D0 is the least significant bit and
the first data bit in a transmit or receive serial data
stream.
Data Set Ready (active LOW). These inputs are
associated with individual UART channels, A through D.
A logic 0 on this pin indicates the modem or data set is
powered-on and is ready for data exchange with the
UART. This pin has no effect on the UART’s transmit or
receive operation.
Data Terminal Ready (active LOW). These outputs
are associated with individual UART channels, A
through D. A logic 0 on this pin indicates that the
SC16C554B/554DB is powered-on and ready. This pin
can be controlled via the Modem Control Register.
Writing a logic 1 to MCR[0] will set the DTR output to
logic 0, enabling the modem. This pin will be a logic 1
after writing a logic 0 to MCR[0], or after a reset. This
pin has no effect on the UART’s transmit or receive
operation.
Signal and power ground.
Interrupt A, B, C, D (active HIGH). This function is
associated with the 16 mode only. These pins provide
individual channel interrupts INTA to INTD.
INTA to INTD are enabled when MCR[3] is set to a
logic 1, interrupts are enabled in the Interrupt Enable
Register (IER), and when an interrupt condition exists.
Interrupt conditions include: receiver errors, available
receiver buffer data, transmit buffer empty, or when a
modem status flag is detected. When the 68 mode is
selected, the functions of these pins are re-assigned.
68 mode functions are described under their respective
name/pin headings.
SC16C554B/554DB
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 56