sc16c554dbib64 NXP Semiconductors, sc16c554dbib64 Datasheet - Page 17

• Manufacturer Part Number: sc16c554dbib64
• Description: 5 V, 3.3 V And 2.5 V Quad Uart, 5 Mbit/s Max. With 16-byte Fifos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
SC16C554B_554DB_3
Product data sheet
6.2 Internal registers
6.3 FIFO operation
The SC16C554B/554DB provides 12 internal registers for monitoring and control. These
registers are shown in
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control Register
(FCR), line status and control registers (LCR/LSR), modem status and control registers
(MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user
accessible Scratchpad Register (SPR). Register functions are more fully described in the
following paragraphs.
Table 5:
[1]
[2]
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. With SC16C554B devices, the user can set the receive trigger level, but not
the transmit trigger level. The receiver FIFO section includes a time-out function to ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached.
Table 6:
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Selected trigger level
(characters)
1
4
8
14
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
A1
0
0
1
1
0
0
1
1
0
0
Internal registers decoding
Flow control mechanism
A0
0
1
0
1
0
1
0
1
0
1
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Rev. 03 — 1 September 2005
Table
Read mode
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
5. These registers function as data holding registers
INT pin activation
1
4
8
14
[2]
SC16C554B/554DB
Negate RTS
4
8
12
14
Write mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
[1]
Assert RTS
1
4
8
10
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