sc16c852viet NXP Semiconductors, sc16c852viet Datasheet - Page 16

• Manufacturer Part Number: sc16c852viet
• Description: Sc16c852v 1.8 V Dual Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And Xscale Vlio Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C852V_4
Product data sheet
6.10 DMA operation
6.11 Loopback mode
The SC16C852V FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYx and TXRDYx
output pins.
Remark: DMA pins are not available on the TFBGA36 package.
Table 7.
[1]
Table 8.
[1]
The internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally
(see
In the Loopback mode, the transmitter output (TXA/TXB) and the receiver input
(RXA/RXB) are disconnected from their associated interface pins, and instead are
connected together internally. The CTSx, DSRx, CDx, and RIx are disconnected from
their normal modem control inputs pins, and instead are connected internally to RTS,
DTR, MCR[3] (OP2A/OP2B) and MCR[2] (OP1A/OP1B). Loopback test data is entered
into the transmit holding register via the user data bus interface, D[7:0]. The transmit
UART serializes the data and passes the serial data to the receive UART via the internal
loopback connection. The receive UART converts the serial data back into parallel data
that is then made available at the user data interface D[7:0]. The user optionally compares
the received data to the initial transmitted data for verifying error-free operation of the
UART TX/RX circuits.
In this mode the interrupt pins are 3-stated, therefore the software must use polling
method (see
Non-DMA mode
1 = FIFO empty
0 = at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level, or time-out occurs
Non-DMA mode
1 = at least 1 byte in FIFO 0-to-1 transition when FIFO becomes full
0 = FIFO empty
Receive FIFO becomes full at 32 bytes when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH
or FLWCNTL contains any value other than 0x00 (extended mode) then the receive FIFO becomes full at
128 bytes.
Transmit FIFO becomes full at 32 byte when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH
or FLWCNTL contains any value other than 0x00 (extended mode) then the transmit FIFO becomes full at
128 byte.
Figure
Effect of DMA mode on state of RXRDYx pin
Effect of DMA mode on state of TXRDYx pin
9). MCR[3:0] register bits are used for controlling loopback diagnostic testing.
Table 7
Section
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
and
7.2.2) to send and receive data.
Rev. 04 — 14 January 2008
Table 8
DMA mode
0-to-1 transition when FIFO empties
DMA mode
1-to-0 transition when FIFO has at least one empty location
show this.
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SC16C852V
© NXP B.V. 2008. All rights reserved.
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