m1a3pe1500 Actel Corporation, m1a3pe1500 Datasheet
m1a3pe1500
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m1a3pe1500 Summary of contents
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... True Dual-Port SRAM (except ×18) • 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz ® ARM Processor Support in ProASIC3E FPGAs • M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available with or without Debug A3PE600 A3PE1500 M1A3PE1500 600 k 1.5 M 13,824 38,400 108 Yes 6 ...
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... FG256 and FG484 are footprint-compatible packages. 5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (V minibank (group of I/Os). 6. "G" indicates RoHS-compliant packages. Refer to the the "G" in the part number A3PE600 A3PE1500 M1A3PE1500 I/O Types 147 65 147 165 79 – ...
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... System Gates A3PE1500 = 1,500,000 System Gates A3PE3000 = 3,000,000 System Gates ProASIC3E Devices with Cortex-M1 M1A3PE1500 = 1,500,000 System Gates M1A3PE3000 = 3,000,000 System Gates * The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The – ...
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... I = Industrial temperature range: –40°C to 85°C ambient temperature References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx A3PE600 A3PE1500 M1A3PE1500 – – – 1 Std. ✓ ...
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ProASIC3E Device Family Overview General Description ProASIC3E, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASIC devices the advantage of being a secure, low-power, single-chip solution that is live at ...
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ProASIC3E Device Family Overview valuable IP is protected and secure, making remote ISP possible. An ProASIC3E device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, ...
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Advanced Architecture The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The ProASIC3E device consists of five distinct and programmable architectural features page 3): • FPGA VersaTiles • Dedicated FlashROM • Dedicated SRAM/FIFO memory • Extensive CCCs and PLLs ...
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ProASIC3E Device Family Overview VersaTiles The ProASIC3E core consists of VersaTiles, which have been enhanced beyond the ProASIC core tiles. The ProASIC3E VersaTile supports the following: • All 3-input logic functions—LUT-3 equivalent • Latch with clear or set • D-flip-flop ...
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SRAM and FIFO ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variable- aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have ...
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ProASIC3E Device Family Overview Pro I/Os with Advanced I/O Standards The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O ...
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Previous Version Advanced v0.5 In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was (April 2006) changed for the FG484 and FG676 packages. Advanced v0.4 BLVDS and M-LDVS are new I/O standards added to the datasheet. (October ...
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ProASIC3E DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some ...
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ProASIC3E DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions Symbol T Ambient temperature core supply voltage CC V JTAG DC voltage JTAG V Programming voltage PUMP V Analog power supply (PLL) CCPLL 2 ...
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Table 2-4 • Overshoot and Undershoot Limits Average V V and VMV as a Percentage of Clock Cycle CCI 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration ...
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ProASIC3E DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until V brownout activation levels. The V on page ...
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Thermal Characteristics Introduction The temperature variable in Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient ...
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ProASIC3E DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-7 • Quiescent Supply Current Characteristics Typical (25°C) Maximum (Commercial) Maximum (Industrial) Notes Includes PUMP CCI shown in Table ...
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Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued) Differential LVDS/BLVDS/M-LVDS LVPECL Notes the static power (where applicable) measured on VMV. DC2 the total dynamic power ...
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ProASIC3E DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices Parameter P Clock contribution of a Global Rib AC1 P Clock contribution of a Global ...
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Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation methodology described below uses the ...
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ProASIC3E DC and Switching Characteristics Combinatorial Cells Contribution— C-CELL C-CELL N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in 1 ...
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Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means that this net switches at ...
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ProASIC3E DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL 0.24 ns ICLKQ t = 0.26 ns ISUD Input LVTTL/LVCMOS Clock I/O ...
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PY PAD t = MAX DIN V trip PAD 50 GND PY (R) t PYS (R) DIN GND Figure 2-3 • Input Buffer Timing Model and Delays (example) ProASIC3E DC and Switching Characteristics t D ...
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ProASIC3E DC and Switching Characteristics D CLK D From Array I/O Interface D DOUT PAD Figure 2-4 • Output Buffer Model and Delays (example DOUT Q DOUT t = MAX MAX(t DOUT ...
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EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD V trip 50 EOUT ( 50% EOUT t ZLS PAD ...
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ProASIC3E DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-13 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial ...
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Table 2-14 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 ...
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ProASIC3E DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-15 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS ...
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Table 2-17 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: T Worst-Case V = 3.0 V CCI I/O Standard 3.3 V LVTTL / 12 High 35 3.3 V LVCMOS 2.5 V LVCMOS 12 High 35 ...
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ProASIC3E DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-18 • Input Capacitance Symbol C Input capacitance IN C Input capacitance on the clock pin INCLK Table 2-19 • I/O Output Buffer Maximum Resistances Standard 3.3 V LVTTL / ...
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Table 2-19 • I/O Output Buffer Maximum Resistances Standard HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on V CCI board ...
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ProASIC3E DC and Switching Characteristics Table 2-21 • I/O Short Currents I 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS * T = 100°C J The length of time an I/O can ...
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Table 2-23 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers Input Buffer Configuration 3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 2.5 V LVCMOS (Schmitt trigger mode) 1.8 V LVCMOS (Schmitt trigger mode) 1.5 V LVCMOS ...
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ProASIC3E DC and Switching Characteristics Test Point Datapath Figure 2-6 • AC Loading Table 2-26 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) 0 3.3 * Measuring point = V . See Table 2-15 ...
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Table 2-28 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Drive Speed Strength Grade DOUT –F 0.79 13.22 0.05 1.44 1.88 Std. 0.66 11.01 0.04 1.20 1.57 –1 0.56 ...
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ProASIC3E DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table ...
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Timing Characteristics Table 2-31 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: T Drive Speed Strength Grade DOUT –F 0.79 10.59 0.05 1.82 1.99 Std. 0.66 8.82 0.04 1.51 1.66 –1 0.56 7.50 0.04 ...
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ProASIC3E DC and Switching Characteristics Table 2-32 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Drive Speed Strength Grade t t DOUT –F 0.79 14.42 0.05 1.82 1.99 Std. 0.66 12.00 0.04 1.51 1.66 –1 0.56 ...
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V LVCMOS Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-33 • Minimum and ...
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ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-35 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: T Drive Speed Strength Grade t t DOUT –F 0.79 14.54 0.05 1.74 2.29 Std. 0.66 12.10 0.04 1.45 1.91 ...
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Table 2-36 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Drive Speed Strength Grade DOUT –F 0.79 19.03 0.05 1.74 2.29 Std. 0.66 15.84 0.04 1.45 1.91 –1 0.56 13.47 0.04 1.23 1.62 ...
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ProASIC3E DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output ...
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Timing Characteristics Table 2-39 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: T Drive Speed Strength Grade DOUT –F 0.79 10.25 0.05 2.04 2.58 Std. 0.66 8.53 0.04 1.70 2.14 –1 0.56 7.26 0.04 ...
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ProASIC3E DC and Switching Characteristics Table 2-40 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: T Drive Speed Strength Grade t t DOUT –F 0.79 16.95 0.05 2.04 2.58 Std. 0.66 14.11 0.04 1.70 2.14 –1 0.56 ...
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V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-41 • Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI ...
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ProASIC3E DC and Switching Characteristics Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 3.3 V. Table 2-44 • Minimum ...
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V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 2.5 V. Table 2-47 • Minimum and Maximum DC Input and Output Levels 2.5 ...
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ProASIC3E DC and Switching Characteristics 3.3 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 3.3 V. Table 2-50 • Minimum and Maximum ...
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V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 2.5 V. Table 2-53 • Minimum and Maximum DC Input and Output Levels ...
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ProASIC3E DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-56 • ...
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HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push- pull output buffer. Table 2-59 • Minimum and Maximum DC ...
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ProASIC3E DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-62 • Minimum and ...
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SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-65 • Minimum and Maximum DC Input and Output ...
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ProASIC3E DC and Switching Characteristics SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-68 • Minimum and ...
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SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-71 • Minimum and Maximum DC Input and Output ...
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ProASIC3E DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by the Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can ...
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Table 2-74 • LVDS Minimum and Maximum DC Input and Output Levels DC Parameter Description V Supply Voltage CCI V Output Low Voltage OL V Output High Voltage Output Lower Current Output High Current ...
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ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-76 • LVDS Commercial-Case Conditions: T Speed Grade –F Std. –1 –2 Note: For specific junction temperature and voltage supply levels, refer to values. BLVDS/M-LVDS Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS) ...
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LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the ...
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ProASIC3E DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset Data C Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-24 ...
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Table 2-80 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output Data Register OHD t Enable ...
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ProASIC3E DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Data CC Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-25 • Timing ...
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Table 2-81 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output Data Register OHD t Enable ...
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ProASIC3E DC and Switching Characteristics Input Register 50% CLK 50% 1 Data Enable 50% t IHE t Preset ISUE Clear Out_1 Figure 2-26 • Input Register Timing Diagram Timing Characteristics Table 2-82 • Input Data Register Propagation Delays Commercial-Case Conditions: ...
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Output Register 50% 50% CLK 50% 1 Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-27 • Output Register Timing Diagram Timing Characteristics Table 2-83 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q ...
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ProASIC3E DC and Switching Characteristics Output Enable Register 50% CLK 50% 1 D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT Figure 2-28 • Output Enable Register Timing Diagram Timing Characteristics Table 2-84 • Output Enable Register Propagation Delays ...
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DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-29 • Input DDR Timing Model Table 2-85 • Parameter Definitions Parameter Name t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t Data Setup ...
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ProASIC3E DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-30 • Input DDR Timing Diagram Timing Characteristics Table 2-86 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out ...
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Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-31 • Output DDR Timing Model Table 2-87 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t Clear Removal DDROREMCLR t Clear ...
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ProASIC3E DC and Switching Characteristics CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-32 • Output DDR Timing Diagram Timing Characteristics Table 2-88 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter ...
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VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3E library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e, and ...
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ProASIC3E DC and Switching Characteristics OUT GND V CC OUT Figure 2-34 • Timing Model and Waveforms NAND2 or Any Combinatorial Logic t = MAX ...
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Timing Characteristics Table 2-89 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell Equation INV AND2 · B NAND2 Y = !(A · B) OR2 NOR2 ...
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ProASIC3E DC and Switching Characteristics 50% CLK 50% Data EN 50 PRE SUE CLR Out Figure 2-36 • Timing Model and Waveforms Timing Characteristics Table 2-90 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the ...
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Global Resource Characteristics A3PE600 Clock Tree Topology Clock delays are device-specific. The global tree presented in device used to drive all D-flip-flops in the device. CCC Figure 2-37 • Example of Global Tree Use in an A3PE600 Device ...
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ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-91 • A3PE600 Global Resource Commercial-Case Conditions: T Parameter Description t Input LOW Delay for Global Clock RCKL t Input HIGH Delay for Global Clock RCKH t Minimum Pulse Width HIGH for ...
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Table 2-93 • A3PE3000 Global Resource Commercial-Case Conditions: T Parameter Description t Input LOW Delay for Global Clock RCKL t Input HIGH Delay for Global Clock RCKH t Minimum Pulse Width HIGH for Global Clock RCKMPWH t Minimum Pulse Width ...
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ProASIC3E DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-94 • ProASIC3E CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks Serial Clock ...
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Output Signal Note: Peak-to-peak jitter measurements are defined by T Figure 2-38 • Peak-to-Peak Jitter Definition ProASIC3E DC and Switching Characteristics T T period_max period_min = T – T peak-to-peak period_max period_min v1 ...
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ProASIC3E DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-39 • RAM Models RAM4K9 RADDR8 ADDRA11 DOUTA8 RADDR7 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA ...
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Timing Waveforms t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-40 • RAM Read for Pass-Through Output t CKH CLK ADD 0 t ...
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ProASIC3E DC and Switching Characteristics t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-42 • RAM Write, Output Retained (WMODE = 0) CLK ADD ...
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CLK1 ADD1 DI1 1 t CCKH CLK2 WEN_B1 WEN_B2 ADD2 DI2 D DO2 D (pass-through) DO2 D (pipelined) Figure 2-44 • Write Access after Write onto Same Address ProASIC3E ...
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ProASIC3E DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DO2 (pass-through) DO2 (pipelined) Figure 2-45 • Read Access after Write onto Same Address ...
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CLK1 ADD1 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 A D DI2 WEN_B2 Figure 2-46 • Write Access after Read onto Same Address t CKH CLK ...
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ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-95 • RAM4K9 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup ...
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Table 2-96 • RAM512X18 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REB_B, WEN_B Hold Time ENH t Input Data (DI) Setup Time DS t Input Data ...
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ProASIC3E DC and Switching Characteristics FIFO Figure 2-48 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 ...
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Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-49 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-50 • FIFO EMPTY Flag and AEMPTY Flag Assertion ProASIC3E ...
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ProASIC3E DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-51 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (EMPTY) (Address Counter) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY ...
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Timing Characteristics Table 2-97 • FIFO Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS t ...
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ProASIC3E DC and Switching Characteristics Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-54 • Timing Diagram Timing Characteristics Table 2-98 • Embedded FlashROM Access Time Parameter t Address Setup Time SU t Address Hold ...
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Part Number and Revision Date Part Number 51700098-002-2 Revised June 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.1 The title of Table 2-4 · Overshoot ...
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ProASIC3E DC and Switching Characteristics Previous Version Advanced v0.6 Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E (continued) Devices was updated. Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for ...
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Previous Version Advanced v0.4 PCI-X 3.3 V was added to the Compatible Standards for 3 Table 2- (continued) 11 • VCCI Voltages and Compatible Standards Table 2-35 • ProASIC3E I/O Features was updated. The "Double Data Rate (DDR) ...
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ProASIC3E DC and Switching Characteristics Previous Version Advanced v0.4 The "DC and Switching Characteristics" chapter was updated with new (continued) information. Table 3-6 was updated. In Table 3-10, PAC4 was updated. Table 3-19 was updated. The note in Table 3-24 ...
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Package Pin Assignments 208-Pin PQFP 208 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 208-Pin PQFP v1.5 ProASIC3E Packaging ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PE600 Function 1 GND 2 GNDQ 3 VMV7 4 GAB2/IO133PSB7V1 5 GAA2/IO134PDB7V1 6 IO134NDB7V1 7 GAC2/IO132PDB7V1 8 IO132NDB7V1 9 IO130PDB7V1 10 IO130NDB7V1 11 IO127PDB7V1 12 IO127NDB7V1 13 IO126PDB7V0 14 IO126NDB7V0 15 IO124PSB7V0 16 ...
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PQFP Pin Number A3PE600 Function 109 TRST 110 V JTAG 111 VMV3 112 GDA0/IO67NPB3V1 113 GDB0/IO66NPB3V1 114 GDA1/IO67PPB3V1 115 GDB1/IO66PPB3V1 116 GDC0/IO65NDB3V1 117 GDC1/IO65PDB3V1 118 IO62NDB3V1 119 IO62PDB3V1 120 IO58NDB3V0 121 IO58PDB3V0 122 GND 123 V B3 CCI 124 ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PE1500 Function 1 GND 2 GNDQ 3 VMV7 4 GAB2/IO220PSB7V3 5 GAA2/IO221PDB7V3 6 IO221NDB7V3 7 GAC2/IO219PDB7V3 8 IO219NDB7V3 9 IO215PDB7V3 10 IO215NDB7V3 11 IO212PDB7V2 12 IO212NDB7V2 13 IO208PDB7V2 14 IO208NDB7V2 15 IO204PSB7V1 16 ...
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PQFP Pin Number A3PE1500 Function 109 TRST 110 V JTAG 111 VMV3 112 GDA0/IO110NPB3V2 113 GDB0/IO109NPB3V2 114 GDA1/IO110PPB3V2 115 GDB1/IO109PPB3V2 116 GDC0/IO108NDB3V2 117 GDC1/IO108PDB3V2 118 IO105NDB3V2 119 IO105PDB3V2 120 IO101NDB3V1 121 IO101PDB3V1 122 GND 123 V B3 CCI 124 ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PE3000 Function 1 GND 2 GNDQ 3 VMV7 4 GAB2/IO308PSB7V4 5 GAA2/IO309PDB7V4 6 IO309NDB7V4 7 GAC2/IO307PDB7V4 8 IO307NDB7V4 9 IO303PDB7V3 10 IO303NDB7V3 11 IO299PDB7V3 12 IO299NDB7V3 13 IO295PDB7V2 14 IO295NDB7V2 15 IO291PSB7V2 16 ...
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PQFP Pin Number A3PE3000 Function 117 GDC1/IO151PDB3V4 118 IO134NDB3V2 119 IO134PDB3V2 120 IO132NDB3V2 121 IO132PDB3V2 122 GND 123 V B3 CCI 124 GCC2/IO117PSB3V0 125 GCB2/IO116PSB3V0 126 NC 127 IO115NDB3V0 128 GCA2/IO115PDB3V0 129 GCA1/IO114PPB3V0 130 GND 131 V CCPLC 132 ...
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Package Pin Assignments 256-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner ...
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FBGA Pin Number A3PE600 Function A1 GND A2 GAA0/IO00NDB0V0 A3 GAA1/IO00PDB0V0 A4 GAB0/IO01NDB0V0 A5 IO05PDB0V0 A6 IO10PDB0V1 A7 IO12PDB0V2 A8 IO16NDB0V2 A9 IO23NDB1V0 A10 IO23PDB1V0 A11 IO28NDB1V1 A12 IO28PDB1V1 A13 GBB1/IO34PDB1V1 A14 GBA0/IO35NDB1V1 A15 GBA1/IO35PDB1V1 A16 GND B1 GAB2/IO133PDB7V1 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3PE600 Function G13 GCC1/IO50PPB2V1 G14 IO44NDB2V1 G15 IO44PDB2V1 G16 IO49NSB2V1 H1 GFB0/IO119NPB7V0 H2 GFA0/IO118NDB6V1 H3 GFB1/IO119PPB7V0 H4 V COMPLF H5 GFC0/IO120NPB7V0 GND H8 GND H9 GND H10 GND H11 ...
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FBGA Pin Number A3PE600 Function P9 IO82PDB5V0 P10 IO76NDB4V1 P11 IO76PDB4V1 P12 VMV4 P13 TCK P14 V PUMP P15 TRST P16 GDA0/IO67NDB3V1 R1 GEA1/IO102PDB6V0 R2 GEA0/IO102NDB6V0 R3 GNDQ R4 GEC2/IO99PDB5V2 R5 IO95NPB5V1 R6 IO91NDB5V1 R7 IO91PDB5V1 R8 IO83NDB5V0 R9 ...
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Package Pin Assignments 324-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner 14 13 ...
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FBGA Pin Number A3PE3000 FBGA A1 GND A2 IO08NDB0V0 A3 IO08PDB0V0 A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO12PDB0V1 A7 GND A8 IO32NDB0V3 A9 IO32PDB0V3 A10 IO42PPB1V0 A11 IO52NPB1V1 A12 GND A13 IO66NDB1V3 A14 IO72NDB1V3 A15 IO72PDB1V3 A16 IO74NDB1V4 A17 IO74PDB1V4 ...
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Package Pin Assignments 324-Pin FBGA Pin Number A3PE3000 FBGA G1 GND G2 IO287PDB7V1 G3 IO287NDB7V1 G4 IO283PPB7V1 CCI G6 IO279PDB7V0 G7 IO291NPB7V2 IO26NDB0V3 G10 IO34NDB0V4 G11 V CC G12 IO94NPB2V1 G13 IO98PDB2V2 G14 ...
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FBGA Pin Number A3PE3000 FBGA N1 IO247NDB6V1 N2 IO247PDB6V1 N3 IO251NPB6V2 N4 GEC0/IO236NDB6V0 N5 V COMPLE N6 IO212NDB5V2 N7 IO212PDB5V2 N8 IO192NPB4V4 N9 IO174PDB4V2 N10 IO170PDB4V2 N11 GDA2/IO154PPB4V0 N12 GDB2/IO155PPB4V0 N13 GDA1/IO153PPB3V4 N14 V COMPLD N15 GDB0/IO152NDB3V4 N16 GDB1/IO152PDB3V4 ...
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Package Pin Assignments 484-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner ...
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FBGA Pin Number A3PE600 Function A1 GND A2 GND CCI A4 IO06NDB0V1 A5 IO06PDB0V1 A6 IO08NDB0V1 A7 IO08PDB0V1 A8 IO11PDB0V1 A9 IO17PDB0V2 A10 IO18NDB0V2 A11 IO18PDB0V2 A12 IO22PDB1V0 A13 IO26PDB1V0 A14 IO29NDB1V1 A15 IO29PDB1V1 A16 IO31NDB1V1 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE600 Function C21 NC C22 V B2 CCI GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO05PDB0V0 D9 IO10PDB0V1 D10 IO12PDB0V2 D11 IO16NDB0V2 D12 IO23NDB1V0 D13 ...
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FBGA Pin Number A3PE600 Function H16 GBC2/IO38PDB2V0 H17 IO37NDB2V0 H18 IO41NDB2V0 H19 IO41PDB2V0 H20 V CC H21 NC H22 NC J1 IO123NDB7V0 J2 IO123PDB7V0 IO124PDB7V0 J5 IO125PDB7V0 J6 IO126PDB7V0 J7 IO130NDB7V1 CCI J9 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE600 Function N13 GND N14 V CC N15 V B3 CCI N16 IO54NPB3V0 N17 IO57NPB3V0 N18 IO55NPB3V0 N19 IO57PPB3V0 N20 NC N21 IO56NDB3V0 N22 IO58PDB3V0 IO111PDB6V1 P3 IO115NPB6V1 P4 IO113NPB6V1 ...
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FBGA Pin Number A3PE600 Function V9 IO91NDB5V1 V10 IO91PDB5V1 V11 IO83NDB5V0 V12 IO83PDB5V0 V13 IO77NDB4V1 V14 IO77PDB4V1 V15 IO69NDB4V0 V16 GDB2/IO69PDB4V0 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 IO63NDB3V1 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE1500 Function A1 GND A2 GND CCI A4 IO05NDB0V0 A5 IO05PDB0V0 A6 IO11NDB0V1 A7 IO11PDB0V1 A8 IO15PDB0V1 A9 IO17PDB0V2 A10 IO27NDB0V3 A11 IO27PDB0V3 A12 IO32PDB1V0 A13 IO43PDB1V1 A14 IO47NDB1V1 A15 ...
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FBGA Pin Number A3PE1500 Function C21 NC C22 V B2 CCI GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO09PDB0V1 D9 IO13PDB0V1 D10 IO21PDB0V2 D11 IO31NDB0V3 D12 IO37NDB1V0 D13 IO37PDB1V0 D14 IO49NDB1V2 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE1500 Function H19 IO67PDB2V1 H20 V CC H21 VMV2 H22 IO74PSB2V2 J1 IO212NDB7V2 J2 IO212PDB7V2 J3 VMV7 J4 IO206PDB7V1 J5 IO204PDB7V1 J6 IO210PDB7V2 J7 IO215NDB7V3 CCI J9 GND J10 V ...
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FBGA Pin Number A3PE1500 Function N17 IO91NPB3V0 N18 IO90NPB3V0 N19 IO91PPB3V0 N20 GNDQ N21 IO93NDB3V0 N22 IO95PDB3V1 IO183PDB6V2 P3 IO187NPB6V2 P4 IO184NPB6V2 P5 IO176PPB6V1 P6 IO182PDB6V1 P7 IO182NDB6V1 CCI P9 GND P10 V ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE1500 Function V14 IO123PDB4V1 V15 IO112NDB4V0 V16 GDB2/IO112PDB4V0 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 IO105NDB3V2 GND W5 IO165NDB5V3 W6 GEB2/IO165PDB5V3 W7 ...
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FBGA Pin Number A3PE3000 Function A1 GND A2 GND CCI A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO16NDB0V1 A7 IO16PDB0V1 A8 IO18PDB0V2 A9 IO24PDB0V2 A10 IO28NDB0V3 A11 IO28PDB0V3 A12 IO46PDB1V0 A13 IO54PDB1V1 A14 IO56NDB1V1 A15 IO56PDB1V1 A16 IO64NDB1V2 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE3000 Function C21 IO94PPB2V1 C22 V B2 CCI D1 IO293PDB7V2 D2 IO303NDB7V3 D3 IO305NDB7V3 D4 GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO20PDB0V2 D9 IO22PDB0V2 D10 IO30PDB0V3 D11 IO38NDB0V4 D12 IO52NDB1V1 D13 ...
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FBGA Pin Number A3PE3000 Function H19 IO100PDB2V2 H20 V CC H21 VMV2 H22 IO105PDB2V2 J1 IO285NDB7V1 J2 IO285PDB7V1 J3 VMV7 J4 IO279PDB7V0 J5 IO283PDB7V1 J6 IO281PDB7V0 J7 IO287NDB7V1 CCI J9 GND J10 V CC J11 V ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3PE3000 Function N17 IO132NPB3V2 N18 IO117NPB3V0 N19 IO132PPB3V2 N20 GNDQ N21 IO126NDB3V1 N22 IO128PDB3V1 P1 IO247PDB6V1 P2 IO253PDB6V2 P3 IO270NPB6V4 P4 IO261NPB6V3 P5 IO249PPB6V1 P6 IO259PDB6V3 P7 IO259NDB6V3 CCI P9 ...
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FBGA Pin Number A3PE3000 Function V15 IO155NDB4V0 V16 GDB2/IO155PDB4V0 V17 TDI V18 GNDQ V19 TDO V20 GND V21 IO146PDB3V4 V22 IO142NDB3V3 W1 IO239NDB6V0 W2 IO237PDB6V0 W3 IO230PSB5V4 W4 GND W5 IO232NDB5V4 W6 GEB2/IO232PDB5V4 W7 IO231NDB5V4 W8 IO214NDB5V2 W9 IO214PDB5V2 ...
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Package Pin Assignments 676-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx ...
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FBGA Pin Number A3PE1500 Function A1 GND A2 GND A3 GAA0/IO00NDB0V0 A4 GAA1/IO00PDB0V0 A5 IO06NDB0V0 A6 IO09NDB0V1 A7 IO09PDB0V1 A8 IO14NDB0V1 A9 IO14PDB0V1 A10 IO22NDB0V2 A11 IO22PDB0V2 A12 IO26NDB0V3 A13 IO26PDB0V3 A14 IO30NDB0V3 A15 IO30PDB0V3 A16 IO34NDB1V0 A17 IO34PDB1V0 ...
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Package Pin Assignments 676-Pin FBGA Pin Number A3PE1500 Function AD5 IO162PDB5V3 AD6 IO160NDB5V3 AD7 IO161NDB5V3 AD8 IO154NDB5V2 AD9 IO148PDB5V1 AD10 IO151PDB5V2 AD11 IO144PDB5V1 AD12 IO140PDB5V0 AD13 IO143PDB5V1 AD14 IO141PDB5V0 AD15 IO134PDB4V2 AD16 IO133PDB4V2 AD17 IO127PDB4V2 AD18 IO130PDB4V2 AD19 IO126PDB4V1 AD20 ...
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FBGA Pin Number A3PE1500 Function C9 IO10PDB0V1 C10 IO16PDB0V2 C11 IO20PDB0V2 C12 IO24PDB0V3 C13 IO23PDB0V2 C14 IO28PDB0V3 C15 IO31PDB0V3 C16 IO32NDB1V0 C17 IO36NDB1V0 C18 IO37NDB1V0 C19 IO45NDB1V1 C20 IO42PPB1V1 C21 IO46NPB1V1 C22 IO48NPB1V2 C23 GBB0/IO56NPB1V3 C24 VMV1 C25 GBC2/IO60PDB2V0 ...
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Package Pin Assignments 676-Pin FBGA Pin Number A3PE1500 Function G13 IO21NDB0V2 G14 IO27PDB0V3 G15 IO35NDB1V0 G16 IO39PDB1V0 G17 IO51NDB1V2 G18 IO53NDB1V2 G19 V B1 CCI G20 GBA2/IO58PPB2V0 G21 GNDQ G22 IO64NDB2V1 G23 IO64PDB2V1 G24 IO72PDB2V2 G25 IO72NDB2V2 G26 IO78PDB2V2 H1 ...
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FBGA Pin Number A3PE1500 Function L17 GND L18 V CC L19 V B2 CCI L20 IO67PDB2V1 L21 IO67NDB2V1 L22 IO71PDB2V2 L23 IO71NDB2V2 L24 GNDQ L25 IO82PDB2V3 L26 IO84NDB2V3 M1 IO198NPB7V0 M2 IO202PDB7V1 M3 IO202NDB7V1 M4 IO206NDB7V1 M5 IO206PDB7V1 M6 ...
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Package Pin Assignments 676-Pin FBGA Pin Number A3PE1500 Function R21 IO89NDB3V0 R22 GCB2/IO89PDB3V0 R23 IO90NDB3V0 R24 GCC2/IO90PDB3V0 R25 IO91PDB3V0 R26 IO91NDB3V0 T1 IO186PDB6V2 T2 IO185NDB6V2 T3 GNDQ T4 IO180PDB6V1 T5 IO180NDB6V1 T6 IO188NDB6V2 T7 GFB2/IO188PDB6V2 CCI T9 ...
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FBGA Pin Number A3PE1500 Function W25 IO96PDB3V1 W26 IO94NDB3V0 Y1 IO175NDB6V1 Y2 IO175PDB6V1 Y3 IO173NDB6V0 Y4 IO173PDB6V0 Y5 GEC1/IO169PPB6V0 Y6 GNDQ Y7 VMV6 CCI Y9 IO163NDB5V3 Y10 IO159PDB5V3 Y11 IO153PDB5V2 Y12 IO147PDB5V1 Y13 IO139PDB5V0 Y14 IO137PDB5V0 ...
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Package Pin Assignments 896-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx ...
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FBGA Pin Number A3PE3000 Function A2 GND A3 GND A4 IO14NPB0V1 A5 GND A6 IO07NPB0V0 A7 GND A8 IO09NDB0V1 A9 IO17NDB0V2 A10 IO17PDB0V2 A11 IO21NDB0V2 A12 IO21PDB0V2 A13 IO33NDB0V4 A14 IO33PDB0V4 A15 IO35NDB0V4 A16 IO35PDB0V4 A17 IO41NDB1V0 A18 IO43NDB1V0 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000 Function AC21 IO164PDB4V1 AC22 IO162PPB4V1 AC23 GND AC24 V COMPLD AC25 IO150NDB3V4 AC26 IO148NDB3V4 AC27 GDA1/IO153PDB3V4 AC28 IO145NDB3V3 AC29 IO143NDB3V3 AC30 IO137NDB3V2 AD1 GND AD2 IO242NPB6V1 AD3 IO240NDB6V0 AD4 GEC0/IO236NDB6V0 AD5 V ...
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FBGA Pin Number A3PE3000 Function AG9 IO225NPB5V3 AG10 IO223NPB5V3 AG11 IO221PDB5V3 AG12 IO221NDB5V3 AG13 IO205NPB5V1 AG14 IO199NDB5V0 AG15 IO199PDB5V0 AG16 IO187NDB4V4 AG17 IO187PDB4V4 AG18 IO181NDB4V3 AG19 IO171PPB4V2 AG20 IO165NPB4V1 AG21 IO161NPB4V0 AG22 IO159NDB4V0 AG23 IO159PDB4V0 AG24 IO158PPB4V0 AG25 GDB2/IO155PDB4V0 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000 Function AK28 GND AK29 GND B1 GND B2 GND B3 GAA2/IO309PPB7V4 IO14PPB0V1 IO07PPB0V0 B8 IO09PDB0V1 B9 IO15PPB0V1 B10 IO19NDB0V2 B11 IO19PDB0V2 B12 IO29NDB0V3 B13 ...
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FBGA Pin Number A3PE3000 Function E17 IO49PDB1V1 E18 IO50PDB1V1 E19 IO58PDB1V2 E20 IO60NDB1V2 E21 IO77PDB1V4 E22 IO68NDB1V3 E23 IO68PDB1V3 E24 V B1 CCI E25 IO74PDB1V4 E26 V CC E27 GBB1/IO80PPB1V4 E28 V B2 CCI E29 IO82NPB2V0 E30 GND F1 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000 Function J5 IO295NDB7V2 J6 IO299NDB7V3 CCI J8 V CCPLA J10 IO04NPB0V0 J11 IO18NDB0V2 J12 IO20NDB0V2 J13 IO20PDB0V2 J14 IO32NDB0V3 J15 IO32PDB0V3 J16 IO42PDB1V0 J17 IO44NDB1V0 J18 ...
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FBGA Pin Number A3PE3000 Function M23 IO104PPB2V2 M24 IO102PDB2V2 M25 IO102NDB2V2 M26 IO95PDB2V1 M27 IO97NDB2V1 M28 IO101NDB2V2 M29 IO103NDB2V2 M30 IO119PDB3V0 N1 IO276PDB7V0 N2 IO278PDB7V0 N3 IO280PDB7V0 N4 IO284PDB7V1 N5 IO279PDB7V0 N6 IO285NDB7V1 N7 IO287NDB7V1 N8 IO281NDB7V0 N9 IO281PDB7V0 ...
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Package Pin Assignments 896-Pin FBGA Pin Number A3PE3000 Function T11 V CC T12 GND T13 GND T14 GND T15 GND T16 GND T17 GND T18 GND T19 GND T20 V CC T21 V B3 CCI T22 IO109NPB2V3 T23 IO116NDB3V0 T24 ...
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FBGA Pin Number A3PE3000 Function W29 IO131PDB3V2 W30 IO123NDB3V1 Y1 IO266PDB6V4 Y2 IO250PDB6V2 Y3 IO250NDB6V2 Y4 IO246PDB6V1 Y5 IO247NDB6V1 Y6 IO247PDB6V1 Y7 IO249NPB6V1 Y8 IO245PDB6V1 Y9 IO253NDB6V2 Y10 GEB0/IO235NPB6V0 Y11 V CC Y12 V CC Y13 V CC Y14 ...
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Package Pin Assignments Part Number and Revision Date Part Number 51700098-003-5 Revised June 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.4 The A3PE600 (June 2008) ...
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Previous Version Advanced v0.6 Notes were added to the package diagrams identifying if they were top or (January 2007) bottom view. The A3PE1500 "208-Pin PQFP" table is new. The A3PE1500 "484-Pin FBGA" table is new. The A3PE1500 "A3PE1500 Function" table ...
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... Package Pin Assignments Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as “Product Brief,” “Advanced,” and “Production”. The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) and contains general product information ...
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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court River Court,Meadows Business Park Mountain View, CA Station Approach, Blackwater 94043-4655 USA Camberley Surrey GU17 9AB United Kingdom Phone 650 ...