m1a3pe1500 Actel Corporation, m1a3pe1500 Datasheet - Page 21

• Manufacturer Part Number: m1a3pe1500
• Description: Proasic3e Flash Family Fpgas With Optional Soft Arm Support
• Manufacturer: Actel Corporation

Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For
more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE
software.
The power calculation methodology described below uses the following variables:
Methodology
Total Power Consumption—P
Total Static Power Consumption—P
Total Dynamic Power Consumption—P
Global Clock Contribution—P
Sequential Cells Contribution—P
•
•
•
•
•
•
•
•
P
P
P
P
P
TOTAL
STAT
DYN
CLOCK
S-CELL
The number of PLLs as well as the number and the frequency of each output clock
generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
Enable rates of output buffers—guidelines are provided for typical applications in
Table 2-12 on page
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-12 on page
in the design.
= P
P
P
= P
N
N
N
Table 2-11 on page 2-11
N
Table 2-11 on page 2-11
F
N
P
N
multi-tile sequential cell is used, it should be accounted for as 1.
α
page 2-11
F
CLK
CLK
= P
STAT
DYN
AC1
= N
SPINE
INPUTS
OUTPUTS
ROW
S-CELL
S-CELL
= (P
1
CLOCK
DC1
is the toggle rate of VersaTile outputs—guidelines are provided in
2-11.
STAT
, P
S-CELL
is the global clock signal frequency.
is the global clock signal frequency.
AC1
is the total dynamic power consumption.
is the total static power consumption.
is the number of VersaTile rows used in the design—guidelines are provided in
+ N
is the number of global spines used in the user design—guidelines are provided in
AC2
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as sequential modules in the design. When a
+ P
is the number of I/O input buffers used in the design.
+ P
+ N
.
INPUTS
is the number of I/O output buffers used in the design.
* (P
, P
DYN
S-CELL
SPINE
AC3
AC5
* P
, and P
* P
+ P
+
2-11.
2-11. The calculation should be repeated for each clock domain defined
DC2
α
AC2
C-CELL
1
+ N
/ 2 * P
+ N
AC4
CLOCK
.
.
TOTAL
OUTPUTS
+ P
ROW
are device-dependent.
S-CELL
AC6
NET
STAT
* P
) * F
v1.2
+ P
* P
AC3
DYN
INPUTS
CLK
DC3
+ N
S-CELL
+ P
OUTPUTS
* P
AC4
ProASIC3E DC and Switching Characteristics
+ P
) * F
MEMORY
CLK
+ P
PLL
Table 2-11 on
Table 2-11 on
2 - 9