ht827a0 Holtek Semiconductor Inc., ht827a0 Datasheet - Page 26

• Manufacturer Part Number: ht827a0
• Description: 8-bit Microcontroller With Voice Rom
• Manufacturer: Holtek Semiconductor Inc.

Input/Output ports
The HT827A0 includes 36 bidirectional in-
put/output lines, labeled from PA to PC or PE
which are mapped to the data memories of
[12H], [14H], [16H], [18H] and [1AH], respec-
tively. All of these I/O ports can be used as input
and output operations. For input operation,
these ports are non-latched, i.e., the inputs
must be ready at the T2 rising edge of the in-
struction ²MOV A, [m]² (m=12, 14, 16H, 18H or
1AH). For output operation, all the data are
latched and remain unchanged till the output
latch is re-written.
Each I/O line has its own control register (PAC,
PBC, PCC, PDC and PEC) to control the in-
put/output configuration. With a control regis-
ter, a CMOS output or schmitt trigger input can
be re-configured dynamically (i.e., on-the-fly)
with or without pull-high resistor structures
under a software control. To function as an in-
put, the corresponding latch of a control regis-
ter must write ²1². The pull-high resistance will
be automatically exhibited if the pull-high op-
tion is chosen. The input source also depends on
the control register. If the bit of the control reg-
ister bit ²1², the input will read the pad state. If
SWAPA [ACC];
ORM A, [DATA];
Combine the lower-order
data and
higher-order data
Input/Output ports
26
it is ²0², the contents of the latches will move to
the internal bus. The latter is possible only in
the ²read-modify-write² instruction. For the
output function, CMOS is the only configura-
tion. These control registers are all mapped to
locations 13H, 15H, 17H, 19H, 1BH. The PE
hi-nibble bits are void, this four bits are read as
²0².
These input/output lines stay at a high level or
floating (decided by mask option) after a chip
reset. Each bit of the input/output latches can
be set or cleared by the ²SET[m].i² and
²CLR[m].i² (m=12H, 14H, 16H, 18H, 1AH) in-
structions.
Some instructions will first input data and then
follow the output operations. For instance,
²SET[m].i², ²CLR[m].i², ²CPL[m]², and ²CPLA[m]²
read the entire port state into the CPU, execute
the defined operations (bit-operation), and then
write the results back to the latches or accumula-
tor.
Each line of port A is capable of waking up the
device. The highest four bits of port E are not
physically implemented. A ²0² will return to
reading the highest four bits, but writing them
will result with no operation.
March 15, 2000
HT827A0