as6c2016 Alliance Memory, Inc, as6c2016 Datasheet - Page 6

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as6c2016

Manufacturer Part Number
as6c2016
Description
Static Random Access Memory
Manufacturer
Alliance Memory, Inc
Datasheet

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TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise t
4.t
5.At any given temperature and voltage condition, t
LB#,UB#
Address
Address
CLZ
Dout
Dout
CE#
OE#
FEBRUARY/2008, V 1.c
January 2007
FEBRUARY 2008
, t
BLZ,
t
OLZ
, t
Previous Data Valid
CHZ,
t
BHZ
and t
OHZ
High-Z
are specified with C
t
BLZ
128K X 16 BIT LOW POWER CMOS SRAM
t
CLZ
t
t
AA
AA
t
OLZ
t
ACE
t
BA
CHZ
t
t
Alliance Memory Inc.
RC
RC
t
OE
is less than t
L
= 5pF. Transition is measured ±500mV from steady state.
512K X 8 BIT LOW POWER CMOS SRAM
CLZ
, t
BHZ
Data Valid
.
is less than t
Data Valid
t
OH
t
t
BHZ
CHZ
t
OHZ
BLZ
t
OH
, t
OHZ
is less than t
AA
is the limiting parameter.
High-Z
OLZ.
Page 6 of 13
AS6C2016

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