hsp50415 Intersil Corporation, hsp50415 Datasheet - Page 20

• Manufacturer Part Number: hsp50415
• Description: Wideband Programmable Modulator Wpm
• Manufacturer: Intersil Corporation

BIT NO.
31:24
21:20
BIT NO.
23
22
19
18
11:10
9:6
12
5
4
3
2
1
0
FIFO Frequency Term 4 Loop Filter <7:0>.
FIFO Full Stop Writing
FIFO Empty, Force 0 data
FIFO Threshold Mode
00
01
10
11
FIFO TXEN Zero Data. (Function: If FIFO Reads are gated with TXEN Pin then force data out of FIFO
block to 0x0000 if TXEN is inactive.)
FIFO TXEN Enable Gated Write
0 = TXEN Pin gates writing to FIFO
1 = FIFO writes not gated by TXEN
B
B
B
B
= Enable Thresholds and Force lag accumulator to Limit
2-bit Filter Mode. Input data at 2x rate with ½ # taps used.
Shaping Filter Interpolation
00
01
10
11
Data Bit Width NumBits/2
If Bit 12 = 0,
0000
0001
1110
1111
If Bit 12 = 1,
0000
0001
1110
1111
X/Sin(X) Filter Bypass.
0 = Enable 1 = Bypass
Half Band Filter Enable
0 = Bypass 1 = Enable
Shaping Filter Bypass
0 = Enable 1 = Bypass
Decimate by 2 at output of Shaping Filter
0 = Disable 1 = Enable
Constellation Map Bypass
0 = Enable 1 = Bypass
FIFO Bypass
0 = Enable 1 = Bypass
= Disable Threshold Logic and FIFOUnderFlow / FIFOOverFlow flags
= Enable Thresholds, Disable Symbol Rate Modifications
= Enable Thresholds and Modify Frequency Error Term
B
B
B
B
= reserved
= 4x
= 8x
= 16x
B
B
B
B
B
B
B
B
= 16 bits
= 32 bits
= 15 bits
= 30 bits
= 1 bit
= 2 bits…
= 2 bits
= 4 bits…
20
TABLE 15. DEVICE CONFIGURATION CONTROL (Continued)
B12
-1
TABLE 16. FIFO AND I/O CONTROL
DESCRIPTION
DESCRIPTION
ADDRESS = 01
ADDRESS = 02
HSP50415
H
H
RESET STATE
RESET STATE
0000
00
0
1
0
1
0
1
1
00
00
B
B
0
0
0
0
B
H
B
April 23, 2007
FN4559.6