hsp50415 Intersil Corporation, hsp50415 Datasheet - Page 7

• Manufacturer Part Number: hsp50415
• Description: Wideband Programmable Modulator Wpm
• Manufacturer: Intersil Corporation

The SYMBOL NCO 32-bit Phinc value is adjusted
automatically such that the SYMBOL NCO runs at the input
rate of the interpolating filter, since this is the fastest rate
prior to the FSout rate. Table 1 lists possible filter
configurations of the HSP50415 and the resulting
interpolating filter rate. This resulting rate is affected by rate
adjustments (interpolation) in the previous filter blocks.
Digital Phase Lock Loop
The HSP50415 contains a Digital Phase Lock Loop (DPLL)
that performs symbol tracking to an external symbol clock
(REFCLK). The DPLL consists of a programmable
phase/frequency error detector followed by a loop filter and
lock detector stage. The phase/frequency error detector
block diagram is shown in Figure 2.
The DPLL uses two (integer) counters to give added
frequency programming flexibility. The programmed symbol
rates are functions of the both the REFCLK divider and the
NCO divider (N = NCO divider + 1, see Figure 2), each of
which can be changed separately. As an example, these two
counters can be set to generate a non-integer output (NCO
Symbol rate) frequency (16/3) of the input reference
frequency (REFCLK). In this case NCO divider = 16, and
REFCLK divider =3. If REFCLK is the desired symbol rate,
then the REFCLK divider will be the same value as the NCO
divider. If REFCLK is for example 2x the desired symbol
rate, then the refClk divider will be 2x the NCO divider.
REFCLK is divided down by the REFCLK divider. The
internal symbol clk is divided down by the NCO divider.
When the carry-out of the REFCLK divider is generated, the
symbol NCO is sampled. The phase and frequency (dphi/dt)
should be zero if the two rates are phase and frequency
locked. If not, the sampled phase value is the phaseError.
This value is subtracted from the previous phaseError to
generate the frequency error. Both of these error terms are
input to the loop filter which scales and integrates these error
terms and produces a final symbol nco error term. This final
error term gets added to the SYMBOL NCO to adjust the
symbol rate to try to track to the divided down external
REFCLK input. The loop filter error term must be enabled in
the software for this error term to be added to the symbol
NCO. Otherwise the Digital PLL has no effect on the symbol
rate.
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HSP50415
The minimum value the REFCLK divider and NCO divider
values may be programmed to is the larger of 32/clkDivisor
or 0x04, where clkDivisor is FSout/REFCLKrate. This is due
to the minimum number of system clock (SYSCLK/2) cycles
the loop filter requires to process the new error terms. The
maximum rate of this clock is FSout/4 or 25MHz for FSout of
100MHz. The phaseError and freqError terms are input to
the loop filter block which is a standard lead/lag type second
order loop filter as shown in Figure 3. The loop filter requires
32 clock cycles to process a new error term.
The phaseError is weighted by the lag gain and added to the
freqError weighted by the frequency gain and this sum is
accumulated to give the integral response. The lag
accumulator is compared to upper and lower limits and
forced to the limit value if either limit is exceeded. This keeps
the SYMBOL NCO frequency within the expected symbol
rate uncertainty and limits the pull in range. This accumulator
output is then added to the phaseError weighted by the lead
gain to get a proportional response. This lead term should be
zeroed during initial tracking. The gain values are user
programmable with a mantissa and exponent of the following
format
Gain = 01.MMMM * 2^(EEEEE-17)
where MMMM denotes the 4-bit gain value and EEEEE is
the 5-bit shift value.
The phaseError and freqError signals may be monitored on
the digital outputs for test or the lock detect pin may be used
to monitor the symbol tracking phase error. The lock detect
pin indicates whether the DPLL has phase locked to the
external symbol clock. The lock detect status may also be
used to generate an interrupt event. The lock detect block
diagram is shown in Figure 4.
April 23, 2007
FN4559.6