ml7033 Oki Semiconductor, ml7033 Datasheet
ml7033
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ml7033 Summary of contents
Page 1
... PCM input and output. The ML7033 is designed for single-rail, low power applications. The high integration of the ML7033 reduces the number of external components and overall board size. The ML7033 is best suited for line card applications and provides an easy interface to subscriber line interface circuits (SLIC’s), in particular the Intersil RSLIC ...
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... Semiconductor BLOCK DIAGRAM FEDL7033-02 ML7033 PDN RESET MCK TEST CIDATA1 CIDATA2 DIO DEN EXCK INT F2_1 F1_1 F0_1 E0_1 SWC1 BSEL1 DET1 ALM1 F2_2 F1_2 F0_2 E0_2 SWC2 BSEL2 DET2 ALM2 2/51 ...
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... PIN CONFIGURATION (TOP VIEW) 1 N.C 2 AIN1N 3 GSX1 AOUT1P 4 5 AOUT1N TOUT1 SGC TOUT2 11 AOUT2N 12 AOUT2P 13 GSX2 14 AIN2N 15 N.C 16 64-Pin Plastic QFP FEDL7033-02 ML7033 N.C 48 RESET 47 RSYNC 46 XSYNC 45 PCMOUT 44 PCMOSY 43 PCMIN BCLK 39 MCK 38 V DDD 37 DIO DEN 36 35 EXCK INT 34 33 N.C 3/51 ...
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... Output for SLIC2 Uncommitted Switch Control Digital Ground Call ID Data Input for CH1 Call ID Data Input for CH2 (Leave unconnected) (Leave unconnected) Interrupt Output (from SLIC status) MCU Interface Data Clock Input MCU Interface Data Enable Input MCU Interface Control Data Input/Output FEDL7033-02 ML7033 4/51 ...
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... Mode Control Output to SLIC1 F0 Mode Control Output to SLIC1 F1 Mode Control Output to SLIC1 F2 Output for SLIC1 Uncommitted Switch Control Power Supply for Internal Digital Circuit Power Supply for Internal Analog Circuit CH1 Transmit Op-amp Input Positive (Leave unconnected) GSXn AOUTnN DETn FEDL7033-02 ML7033 5/51 ...
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... LV3 LV2 CH2TG1 CH2TG1 CH2TG1 CH2TG1 CH2 CH1 CH1 TEST3 LOOP0 LOOP1 LOOP0 TEST8 TEST7 MODEn CH1TG2_n PMGnFRQ FEDL7033-02 ML7033 R MODE1 MODE0 R/W ALAW CID CID CID R/W FMT CH2ON CH1ON PMG1 PMG1 PMG1 R/W LV1 LV0 TOUT1 TSA2 TSA1 TSA0 ...
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... XSYNC, RSYNC SHORT (CR0-B4) bit = “0” t PCMOUT DS t PCMOUT DH R Pull-up Resistor, PCMOUT DL C PCMOUT DL1 C Other output pins DL2 C SGC FEDL7033-02 ML7033 Rating Unit –0.3 to +7.0 –0 +0.3 DD –0 +0.3 DD –55 to +150 Min. Typ. Max. Unit 4.75 5.0 5.25 DDA –40 — ...
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... SGC SGC Rise time to 90% of max. level R SG LSG (V Symbol Condition R AINnN, AINnP INX R GSXn LGX C (to SGC) LGX *1 V OGX V Gain = 1 OSGX FEDL7033-02 ML7033 = 4. – Min. Typ. Max. Unit — 23.0 35.0 mA — 16.0 22.0 mA — 25.0 50.0 — 0.1 5.0 –5.0 –0.1 — 0 0.2 ...
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... SGC) TOUTn LTO (to SGC) AOUTnN, AOUTnP, TOUTn LAO AOUTnN, AOUTnP, TOUTn OAO (to SGC) LAO AOUTnN, AOUTnP, TOUTn (to SGC) LAO FEDL7033-02 ML7033 (V = 4. – Min. Typ. Max. 20 — — 10 — — — — 50 — — ...
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... PCMIN to AOUTn 1020 –30 *1 –40 –45 3 –10 GSXn to 1020 –40 PCMOUT –50 –55 3 –10 PCMIN to 1020 –40 AOUTn –50 –55 FEDL7033-02 ML7033 Min. Typ. Max. Unit 25 45 — –0.15 0.15 0.20 Reference dB –0.15 0.02 0.20 –0.15 0.1 0.80 0 0.6 0.80 –0.15 0.04 0.2 Reference –0.15 0.07 0.2 dB –0.15 ...
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... FEDL7033-02 ML7033 (V = 4. – Min. Typ. Max. *1 — dBm0 — 0.511 0.548 0.587 Vrms 0 ...
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... LOAD EXCK EXCK FEDL7033-02 ML7033 (V = 4. – Min. Typ. Max. — — 100 — — 100 — — 100 — — 100 — — 100 — 4 — — ...
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... FEDL7033-02 ML7033 XD4 XD4 ...
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... Linear PCM Mode with LIN (CR0-B3) bit = “1” & Short Frame Sync Mode with SHORT (CR0-B4) bit = “1” 1 BCLK RSYNC PCMIN PCMOUT CH1 Linear DATA PCMOSY Figure 3 PCM Interface Bit Configuration 9 17 CH2 PCM DATA 9 17 CH2 Linear DATA 9 17 CH2 PCM DATA 9 17 CH2 Linear DATA FEDL7033-02 ML7033 14/51 ...
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... Semiconductor SGC, PCMOUT, and AOUT Output Timing Figure 4 SGC, PCMOUT, and AOUT Output Timing FEDL7033-02 ML7033 15/51 ...
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... Figure 5 MCU Serial Interface 16 Figure 6 SLIC Interface 1 (to SLIC) Either ALMn pin or DETn pin,or DEN pin (CR6 and CR13 FEDL7033-02 ML7033 16/51 ...
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... While the device is in power-down mode, or the corresponding channel ( power saving mode, the related outputs are high impedance. Refer to Table 5 for more information. GSX1 R2 AIN1N AIN1P SGC GSX2 R4 AIN2N AIN1P SGC or more. When the AOUTnSEL register bit (CR7-B7/CR14- FEDL7033-02 ML7033 CH1 Gain Gain = R2/R1 10 R1: Variable 1/(2 3.14 30 R1) CH2 Gain Gain = R4/R3 ...
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... V power supply for analog and digital circuits. The V V pin is the power pin for the digital circuits. If these signals are connected together externally, The V DDD must be connected to the V pin in the shortest distance on the printed circuit board. Internal to the ML7033, DDD the V plane is separate from the V DDA To minimize power supply noise ...
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... PCMOSY is asserted to a logic 0 when PCM data is valid on the PCMOUT pin. This includes both normal mode and power-save mode. When PCM data is not being output from the PCMOUT pin (including during power-down mode), this pin goes a logic “1”. This signal is used to control the TRI-STATE Enable of a backplane line-driver. FEDL7033-02 ML7033 19/51 ...
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... Operate 0 1 Operate 0 Operate 1 1 Operate FEDL7033-02 ML7033 ALAW (CR0-B2) bit = “1” (A-law ) ...
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... Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Operate Hi-Z Operate Hi-Z Operate Operate Operate Operate TM series device. Though the output level from the E0_n pin is FEDL7033-02 ML7033 CH1 PCM Data Hi-Z *1 ALL “0” Operate ALL “0” Operate SG SGC MCU Interface pin pin Hi-Z AG level *2 Operate Hi-Z AG level *2 Operate Operate ...
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... TM series SLIC device. A logic “0” on this pin selects the low battery TM series SLIC device. By connecting this pin directly to the FEDL7033-02 ML7033 Description Standby mode Forward battery loop feed Unbalanced ringing mode Reverse battery loop feed Balanced ringing mode Test mode ...
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... B7 to B5), and the E0_n register bits (CR6-B2 /CR13-B2). To avoid the unintended detection of these conditions due to glitches on the DETn signal of the SLIC, the ML7033 is equipped with a debounce timer to hold the DET register bit (CR6-B1/CR13-B1) and the output of the INT pin for a set period, even when an input to the DETn pin changes from a logic “ ...
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... Serial control ports for the MCU interface. These pins are used by an external MCU to access the internal control registers of the ML7033. The DEN pin is the data enable input. The EXCK pin is the data shift clock input. The DIO pin is the address and data input/output. Figure 9 shows the MCU interface input/output timing diagram. ...
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... PDN pin = “1” Normal Operation Figure 10 Power-on Sequence Flow Chart <NOTE> As the ML7033 is equipped with a power-on reset function, initialization of the control registers automatically occurs as the power is turned on, even with the RESET pin = logic “1”. However, if any of input pins are not in a high impedance state, the power-on reset may not function properly ...
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... OFF OFF 1 1 OFF *2 OFF 1 1 OFF * OFF The last output stage is powered. FEDL7033-02 ML7033 ALAW MODE1 MODE0 A-law 1 : Normal operation Register Initialized to default *2 Initialized to default Read/Write possible *2 Read/Write possible Read/Write possible *2 Read/Write possible ...
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... CH1TG1LVn (CR9-B7 to B1) bits is valid, but the CH1TG1_n (CR9-B0/CR11-B7 to B0) bits, the CH1RING (CR11-B3) bit, and the CH1TG1TRPn (CR11-B2 to B0) bits are invalid CIDFMT disabled 0 : disabled 0 : OFF 0 : OFF FEDL7033-02 ML7033 CID CID CH2ON CH1ON enabled 1 : enabled ...
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... Pulse metering tone frequency select for CH1 PMG2 PMG2 PMG1 LV0 TOUT2 FRQ kHz Ramp down time=10ms 1 : TOUT2 pin kHz kHz FEDL7033-02 ML7033 PMG1 PMG1 PMG1 LV1 LV0 TOUT1 kHz kHz kHz 28/51 ...
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... CH1 PCM DATA PCMOSY Slot 0 Figure 12 Example of Time Slot Assignment: CH1 = Slot 0, CH2 = Slot TSA5 TSA4 TSA3 Customized time slot assignment 0 : CH1 9 17 Slot 1 Slot 2 FEDL7033-02 ML7033 TSA2 TSA1 TSA0 CH2 25 33 CH2 PCM DATA Slot 3 29/51 ...
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... … Debounce timer setting for CH1 To avoid the unintended detection of glitches on the DETn signal, the ML7033 is equipped with a debounce timer to hold the DETn (CR6-B1/CR13-B1) bit and the INT output state for a set period, even when the state of the DETn pin changes from logic “1” to logic “0”. Bits determine the debounce timer setting for CH2 ...
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... FEDL7033-02 ML7033 LV1X2 LV1X1 LV1X0 Level (dBm0) 0.0 –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 –8.0 –9.0 –10.0 –11.0 –12.0 –13.0 –14.0 OFF 31/51 ...
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... PDN pin = logic “1”, and 200ns later in the power-down mode with the PDN pin = logic “0” than a change of this bit value. Refer to Figure F0_1 SWC1 BSEL1 switch low battery mode TM FEDL7033-02 ML7033 E0_1 DET1 ALM1 0 — — switch off TM series, the SLIC’s internal 1 : high battery mode TM series, the SLIC’ ...
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... When the SLIC connected to channel 1 is from the Intersil RSLIC can be connected directly to the corresponding output pin of the SLIC device. This allows the user to know whether the SLIC1 is in the normal operating state the thermal shutdown state. FEDL7033-02 ML7033 0 : detected 1 : not detected series, the DET1 pin TM ...
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... FEDL7033-02 ML7033 CH1TG2 CH1TG2 CH1TG2 _8 LV1 LV0 side side 0 : AOUT1 pin 1 : TOUT1 pin Level (dBm0) OFF –12.0 –11.0 –10.0 –9.0 –8.0 –7.0 – ...
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... FEDL7033-02 ML7033 CR8 ...
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... FEDL7033-02 ML7033 CH1TG1 CH1TG1 CH1TG1 _8 LV1 LV0 Level TG1LV0 (dBm0 OFF 0 1 –12 –12 –11 –11.8 ...
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... FEDL7033-02 ML7033 CR10 ...
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... FEDL7033-02 ML7033 CR10 ...
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... CrestFacto 1 Figure 13 Ringing Tone Waveform Table 15 Crest Factor Setting B5/B1 B4/B0 TG1 TRP1 TG1 TRP0 FEDL7033-02 ML7033 CH1TG1 CH1TG1 CH1TG1 TRP2 TRP1 TRP0 Crest Factor OFF 1.225 1.250 1.275 1.300 1 ...
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... LV2R1/ LV2X1 LV2R0/ LV2X0 FEDL7033-02 ML7033 LV2X2 LV2X1 LV2X0 Level (dBm0) 0 0.0 1 –1.0 0 –2.0 1 –3.0 0 –4.0 1 –5.0 0 –6.0 1 –7.0 0 –8.0 1 –9.0 0 –10.0 1 –11.0 0 – ...
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... PDN pin = logic “1”, and 200 ns later in the power-down mode with the PDN pin = logic “0” than a change of this bit value. Refer to Figure 6 for more information F0_2 SWC2 BSEL2 switch low battery mode FEDL7033-02 ML7033 E0_2 DET2 ALM2 switch off TM series device, the internal 1 : high battery mode ...
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... If this bit is cleared, the ALM2 pin is a logic “0”. If this bit is set, the ALM2 pin is a logic “1”. When the SLIC connected to channel Intersil RSLIC ALM2 pin directly to the corresponding output pin of the SLIC device allows the ML7033 to know whether the SLIC is in the normal operating mode thermal shutdown state. FEDL7033-02 ...
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... FEDL7033-02 ML7033 CH2TG2 CH2TG2 CH2TG2 _8 LV1 LV0 side side 0 : AOUT2 pin 1 : TOUT2 pin Level (dBm0) OFF –12.0 –11.0 –10.0 –9.0 – ...
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... FEDL7033-02 ML7033 CR15 ...
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... FEDL7033-02 ML7033 CH2TG1 CH2TG1 CH2TG1 _8 LV1 LV0 Level TG1LV0 (dBm0 OFF 0 1 –12 –12 –11 –11.8 ...
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... FEDL7033-02 ML7033 CR17 ...
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... FEDL7033-02 ML7033 CR17 ...
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... A loop-back test is functional if XSYNC and RSYNC are from the same clock source … LSI test registers for an LSI manufacturer The default alternation is prohibited. When a write action is executed for CR18, set all of these bits to “0” CH1 CH1 TEST3 LOOP1 LOOP0 FEDL7033-02 ML7033 TEST2 TEST1 TEST0 48/51 ...
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... CR19 (LSI manufacturer’s test control CR19 TEST11 TEST10 default … LSI test registers for an LSI manufacturer For manufacturing use only. Both reads and writes to this register are prohibited TEST9 TEST8 TEST7 FEDL7033-02 ML7033 TEST6 TEST5 TEST4 49/51 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL7033-02 (Unit: mm) Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating (J5µm) Package weight (g) 0.87 TYP. Rev. No./Last Revised 6/Feb. 23, 2001 ML7033 50/51 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL7033-02 Copyright 2001 Oki Electric Industry Co., Ltd. ML7033 51/51 ...