ml7033 Oki Semiconductor, ml7033 Datasheet - Page 24

• Manufacturer Part Number: ml7033
• Description: Dual-channel Line Card Codec
• Manufacturer: Oki Semiconductor

The INT pin is released to the logic “1” state in either of the following cases;
(1) (PDN pin = logic “1”) Any one of the ALMn or DETn pins in the logic “0” state transition to the logic “1”
(2) (PDN pin = logic “0”) All of the ALMn or DETn pins in the logic “0” state transition to the logic “1”
(3) Both SLIC 1 control (CR6 register) and SLIC 2 control (CR13 register) are read by the MCU.
Note that the debounce timer, which works when the DETn pin changes from a logic “1” state to a to logic “0”
state, does not work when the pin changes from logic “0” to logic “1”.
DEN, EXCK, DIO
Serial control ports for the MCU interface. These pins are used by an external MCU to access the internal control
registers of the ML7033. The DEN pin is the data enable input. The EXCK pin is the data shift clock input. The
DIO pin is the address and data input/output. Figure 9 shows the MCU interface input/output timing diagram.
Note that EXCK must be a continuous clock of at least 15 pulses or more.
CIDATA1, CIDATA2
The CIDATA1 and CDATA2 data inputs are used for Caller ID generation. While in a Caller ID tone generation
mode with the CIDCHnON register bit set, (CR1-B1/CR1-B0), signals on the CIDATAn pins are modulated in
either the ITU-T V.23 or Bell 202 schemes. The scheme is determined by the CIDFMT register bit (CR1-B2),
and output from the analog output pin(s).
The analog output pins for modulated Caller ID data can be selected by the CHnTG2TX (CR7-B6/CR14-B6),
the CHnTGTOUTn (CR7-B5/CR14-B5), and the AOUTnSEL (CR7-B7/CR14-B7) register bits.
The output level for the modulated Caller ID data can be tuned by the CHnTG1LVn (CR9-B7 to B1/CR16-B7 to
B1) register bits.
TEST
The TEST input is used for testing purposes only during the manufacturing process and has no function once the
testing process is completed. This pin is not used during normal operation of the device and should be kept at a
logic “0” state.
DEN
EXCK
DIO (I)
DEN
EXCK
DIO (O)
1 Semiconductor
state.
state.
W
R
A4
A4
Figure 9 MCU Interface Timing Diagram
Input
A3
A3
A2
A2
A1
A1
Write timing
Read timing
A0
A0
B7
B7
B6
B6
B5
B5
Output
B4
B4
B3
B3
B2
B2
B1
B1
B0
B0
FEDL7033-02
ML7033
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