ml7033 Oki Semiconductor, ml7033 Datasheet - Page 20

• Manufacturer Part Number: ml7033
• Description: Dual-channel Line Card Codec
• Manufacturer: Oki Semiconductor

PDN
Power-down control signal. When PDN is a asserted (logic “0”), both the channel 1 and channel 2 circuits enter
the power-down state. However, even in power-down mode, the state of the control registers is maintained.
Reads and writes to the registers are also possible, and the state of the INT pin also changes in accordance with
inputs from the SLIC devices. This pin is deasserted (logic “1”) by external logic during normal operation.
This power-down function is available even in power saving mode by the MODEn (CR0-B1/CR0-B0) bit.
RESET
An input to reset control registers. By asserting the RESET pin (applying a logic “0”), all control registers are
initialized. During a normal operation mode, set this pin logic “1”.
1 Semiconductor
INPUT/OUTPUT
PDN pin
+Full scale
–Full scale
INPUT/OUTPUT
0
1
1
1
1
Level
+Full scale
–Full scale
Table 2 PCM Codes in 14-bit Linear PCM Mode with the LIN (CR0-B3) bit = “1”
+0
–0
Level
+1
–1
Table 3 State of PCMOUT in 8-bit PCM Mode with LIN (CR0-B3) bit = “0”
0
Table 1 PCM Codes in 8-bit PCM Mode with the LIN (CR0-B3) bit = “0”
MODE1 bit
MSD D2
0/1
0
0
1
1
1
1
0
0
ALAW (CR0-B2) bit = “0” ( -law )
MSD
0
0
0
1
1
0
1
1
0
MODE0 bit
D3
D2
0
1
1
0
1
0
0
1
0
0/1
0
1
0
1
D4
D3
0
1
1
0
1
0
0
1
0
D5
D4
0
1
1
0
1
0
0
1
0
ALAW bit
D6
D5
0/1
0
1
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
D7
D6
0
1
1
0
PCMIN/PCMOUT
1
0
0
1
0
PCMIN/PCMOUT
D8 MSD D2
D7
0
1
1
0
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
1
0
0
1
0
CH2 PCM Data
D8
1
0
0
1
0
Operate
Operate
Operate
Operate
1
1
0
0
Hi-Z *1
ALAW (CR0-B2) bit = “1” (A-law )
D9 D10 D11
1
0
0
1
0
0
1
1
0
1
0
0
1
0
D3 D4
1
0
0
1
0
1
1
0
1
0
0
1
0
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1
1 1 0 1 0 1 0 1
D5
1
0
0
1
D12
CH1 PCM Data
1
0
0
1
0
Operate
Operate
Operate
Operate
Hi-Z *1
D6
0
1
1
0
D13
1
0
0
1
0
FEDL7033-02
D7
1
0
0
1
D14
ML7033
1
1
0
1
0
D8
0
1
1
0
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