m21130 Mindspeed Technologies, m21130 Datasheet - Page 15

• Manufacturer Part Number: m21130
• Description: 68 X 68 3.2 Gbps Crosspoint Switch With Input Equalization
• Manufacturer: Mindspeed Technologies

SCLK
21130-DSH-001-B, 3/27/03
Parallel I/O Overview
Setting the hardware pin Ser/xPar low enables the parallel I/O mode. An 8-bit address bus addresses the register and a bi-directional
8-bit data bus can read and write the register contents. The active low data strobe (xDS) latches (stores) the data in the register on
the rising edge of xDS. The double buffer (ICL/ACL) is transparent to the data (mode 1) when xDS=L, so the SS will change on the
falling edge of xDS. On the rising edge of xDS, the switch state will be stored into the register. The active low pin xCS gates the I/O
and the R/xW gates whether a read or write operation is being performed. During a read operation, the current configuration of the
addressed channel is read back from the device if a read is to an output channel register, regardless of the contents of the ICL.
Serial I/O Overview
To configure the M21130 for the serial programming mode, the hardware pin Ser/xPar must be high. A serial I/O operation is initiated
when xCS transitions from a high state to a low state. Data is shifted in on SDI on the falling edge of SCLK, and shifted out on SDO
on the rising edge of SCLK. A 10-bit sequence addresses a register, as illustrated in
sequence, followed by the Operation Bit (OP) and the 8-bit ADDR (MSB first). For a write operation, an 8-bit DATA (MSB first) directly
follows the last address bit. The start bit is 1 in all cases, and the operation bit is 1 for a read and 0 for a write operation.
Figure 6
On each falling edge of SCLK, the 18-bits consisting of the SB = 1, OP = 0, ADDR, and DATA, are latched into the input shift register.
The rising edge of xCS must occur before the falling edge of SCLK for the last bit. Upon receipt of the last bit, one additional cycle of
SCLK is necessary before the input DATA transfers from the input shift register to the addressed register. If consecutive read/write
cycles are being performed, it is not necessary to insert an extra clock cycle between read/write cycles, however one extra clock cycle
is needed after the last data bit of the final read/write cycle to complete the operation.
Figure 5. Serial Word Format
Figure 6. Serial Write Mode
xCS
SDI
Tens
illustrates the serial Write mode timing diagram. To initiate a Write sequence, xCS goes low before the falling edge of SCLK.
1
wr
Start Bit
T dw
a7
17 16
1
T ds
a6
rw
MSB
Read/Write
15
a5
68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization
a4
Address
T dh
A[7:0]
a3
Mindspeed Technologies™
a2
Tclk
a1
LSB
8
a0
MSB
7
Twclk
d7
d6
Figure
D[7:0]
Data
d5
5. The Start Bit (SB) is first in the bit
d4
LSB
d3
0
d2
d1
Tcs
M21130
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d0
Tch
1