m21130 Mindspeed Technologies, m21130 Datasheet - Page 18

• Manufacturer Part Number: m21130
• Description: 68 X 68 3.2 Gbps Crosspoint Switch With Input Equalization
• Manufacturer: Mindspeed Technologies

21130-DSH-001-B, 3/27/03
with DATA=01h. If the next Write is not to the software reset register, the register will clear and two additional consecutive Writes will
be needed. A third write to the software reset register is required to bring the device out of reset and restore all register settings to
their default values. A Hardware reset has priority over a software reset.
Revision Code
A read from register ADDR=F0h (chip revision) results in a readback of the official chip version.
PRBS TX and RX
The PRBS TX section provides a NRZ PRBS pattern or a 22-bit programmable pattern. The data rate of the PRBS Tx output is
determined by the external clock, ClkTxP/ClkTxN (PCML), which is gated by setting the hardware pin external pin xEnTx=L or by
setting the pwr_tx bit of the PRBS power/enable (ADDR=E0h) register. With xEntx=L, output data updates with each rising edge of
ClkTxP. Note that a value of 01h needs to be written into register address E4h to establish the correct seed for the PRBS patterns.
The single-ended output Trig (ClkTxP/16) can be used as a scope trigger to observe the PRBS patterns. The Trig is a PCML output
with a minimum swing of 150 mV. The Trig pin is designed to drive 50 Ω; however, the backmatch is 200 Ω. Data output is via the
differential DoTxP/DoTxN (PCML) pins. The PRBS Rx section takes in a NRZ PRBS pattern and checks for any bit errors. The user
must provide a phase aligned differential clock and data signal for the PRBS receiver, which can be obtained by passing the data
through a clock and data recovery device and connecting the CDR clock and data outputs to the M21130 PRBS Rx inputs. ClkRxP/
ClkRxN clock and DiRxP/DiRxN data are both gated by the external pin xEnRx or the pwr_rx bit of the PRBS power/enable
(ADDR=E0h) register. The falling edge of ClkRxP is expected near the middle of the data eye as illustrated in
Receiver Program timing parameters are listed in
Table 13. PRBS Receiver Timing
When the PRBS RX detects an error, PError will be high. The first and each subsequent error will increment an internal
8-bit counter (PRBS RX error count register ADDR=E2h). If the errors exceed 256 (counter overflow), the counter will stay at 255 until
a hardware or software reset. To read the RX error counter register requires a WRITE of any value to copy the current contents of the
running error register into the PRBS RX error count register. A subsequent READ yields the error count as of the last WRITE. The RX
reset can be initiated by the xRstRx pin or by the rst_rx bit in the PRBS control (ADDR=E1h) register. Upon reset, the PRBS RX error
counter clears and PError resets.
Figure 8. PRBS Receiver Timing
Parameter
t
T
T
en,
t
s,
w,
h,
RX
RX
RX
RX
CLKRXP/N
DIRXP/N
Rx En setup time before falling edge of CLKRx
Rx setup time before falling edge of CLKRx
Rx hold time after falling edge of CLKRx
Pulse width of CLKRx
xENRX
Description
A
68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization
Table
t
en,RX
Mindspeed Technologies™
13.
B
t
s,RX
C
t
310 ps
h,RX
15 ns
15 ps
95 ps
Min
D
Typical
–30 ps
402 ps
50 ps
—
t
w,RX
E
Figure
M21130
8. The PRBS
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Max
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