m21130 Mindspeed Technologies, m21130 Datasheet - Page 19

• Manufacturer Part Number: m21130
• Description: 68 X 68 3.2 Gbps Crosspoint Switch With Input Equalization
• Manufacturer: Mindspeed Technologies

21130-DSH-001-B, 3/27/03
PRBS RX error count will always contain the current value of the error count register. Dividing the value by the time of the test is a
rough estimate of the bit error rate. If there has been more that 256 errors, the PRBS RX error count register will always read FFh until
cleared.
The PRBS pattern length register (ADDR=E3h) sets the pattern length (n) of a 2
PRBS Rx and D2 is the rxcirc bit. If D2=L, then the first ‘n’ bits check the input pattern. If the first 23-bits are error free, then each
additional error is counted once. If D2=H, the recirculation mode is enabled and the last ‘n’ bits check the n+1 bit. If a bit error did
occur, the error bit would shift through the ‘n’ bits of the reference resulting in multiple error counts due to one error. Bits D3 and D4
(txlen) determine the pattern length of the PRBS TX. For both the rxlen and txlen:
For the 2
(CCITT) Rec. 0.151. The lower pattern is commonly used with commercially available bit error rate testers. The 22-bit pattern is a
repeating user-programmed pattern. The error counter will work with all four patterns.
The TX starting pattern used for all four pattern modes can be user programmed with the three PRBS pattern registers, ADDR=E4
through E6h. ADDR=E4h specifies the first 8-bits (Pattern[0 .. 7] of the user pattern, ADDR=E5h specifies the next 8 bits (Pattern[8 ..
15]), and ADDR=E6h specifies the highest seven bits (Pattern[16 .. 22]). An rst_tx and rst_rx (software) needs to be invoked for both
the RX and TX.
To save power, both the PRBS Tx and Rx can be powered off. The PRBS Power/Enable register, ADDR=E0h, controls these
functions.
Core Power Saving
The CoreCtrl register enables the core power-saving modes. Register CoreCtrl[1] = 0 powers down the switch core and the PRBS Tx/
Rx (default power on).
Register CoreCtrl[0] = 1 enables the SmartPower core control (default).
Smartpower reduces power dissipation by as much as 30% by automatically powering down unused circuitry in the switch core once
a switch configuration has been programmed. When the switch configuration is changed, Smartpower will enable/diable the
necessary mux circuitry within the switch core. The actual power savings will vary across different switch configurations. This process
takes approximately 10 ns to complete and will increase the time required to reconfigure the switch core. In applications where the
switch core will be left in the same state for a relatively long period of time this is typically not an issue and is worth the power savings.
In applications where the minimum switch reconfiguration time is needed, such as packet switching applications, Smartpower can be
disabled through software.
Digital Slope Control
Because high speed interface operation requires high speed rise and fall times through the IC, it is possible to generate jitter with the
digital control. To minimize this effect, and realizing not all applications will require the fastest programming times, slope control
internal registers ADDR=EDh and EEh are provided to set the edge rate with respect to the interface I/O speed. The registers and
functions are listed in
Value 00b produces a 2
Value 01b produces a 2
Value 10b produces a 2
Value 11b produces a repeating 22-bit pattern.
n
-1, the higher bit patterns conform to the specification, Consultative Committee on Industrial Telegraph and Telephony
Table 14
7
15
23
and
-1 pattern with the polynomial D7+D6+1.
-1 pattern with the polynomial D15+D14+1
-1 pattern with the polynomial D23+D18+1
Table
15.
68 x 68 3.2 Gbps Crosspoint Switch with Input Equalization
Mindspeed Technologies™
n
-1 pattern. D1 and D0 (rxlen) set the length of the
M21130
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