am79c981 Advanced Micro Devices, am79c981 Datasheet - Page 18

• Manufacturer Part Number: am79c981
• Description: Integrated Multiport Repeater Plus? Imr+? ??9
• Manufacturer: Advanced Micro Devices

P Partitioning Status. This bit is 0 if the AUI port is
B Bit Rate Error. This bit is set to 1 if there has been
S SQE Test Status. This bit is set to 1 if SQE Test is
L Loop Back Error. The MAU attached to the AUI is
Alternate AUI Port Status
There are three further variations of the above com-
mand, allowing selective clearing of a combination of B,
S, and L bits. They are primarily included for use by the
HIMIB chip. These are:
Alternative 1.
Alternative 2.
Alternative 3.
TP Port Partitioning Status
The partitioning Status of all eight TP ports are ac-
cessed by this command. If a port is disabled, reading it
partitioning status will indicate that it is connected.
1–88
partitioned and 1 if connected.
an instance of FIFO Overflow or Underflow,
caused by data received at the AUI port. This bit is
cleared when the status is read.
detected by the IMR+ chip. This bit is cleared
when the status is read. A MAU attached to a re-
peater must have SQE Test disabled. This bit is
set even if the AUI port is disabled or partitioned.
required to loopback data transmitted to DO onto
the DI circuit. If loopback carrier is not detected by
the IMR+ device, then this bit is set to 1 to report
this condition. This bit is cleared when the status is
read. For a repeater this is the only indication of a
broken or missing MAU.
AMD
SI data:
SO data:
SI data:
SO data:
B is not cleared. S and L are cleared.
SI data:
SO data:
S and L are not cleared. B is cleared.
SI data:
SO data:
None of S, B and L are cleared.
SI data:
SO data:
Pn = 0
Pn = 1
10001111
PBSL0000
10001011
PBSL0000
10001101
PBSL0000
10001001
PBSL0000
10000000
P7.................P0
TP port n partitioned
TP port n connected
PRELIMINARY
Am79C981
Bit Rate Error Status of TP Ports
This allows a single command to be used to report Bit
Rate Error condition (FIFO Overflow or Underflow) of all
Twisted Pair ports. The 8 bits of the output pattern corre-
spond to each of the 8 TP ports, with least significant bit
corresponding to port 0.
The status bit for a port is set to 1 if there has been an
instance when data received from that port has caused
a FIFO error.
All status bits stay set until the status is read.
Link Test Status of TP Ports
The Link Test Status of all eight TP ports are accessed
by this command. A disabled port continues to report
correct Link Test Status. Re-enabling a disabled port
causes the port to be placed into Link Test Fail state.
This ensures that packet fragments received on the port
are not repeated to the rest of the network.
Receive Polarity Status of TP Ports
The statuses of all eight TP port polarities are accessed
with this command. The IMR+ chip has the ability to de-
tect and correct reversed polarity on the TP ports’
RXD+/– pins. If the polarity is detected as reversed for a
TP port, then the IMR+ chip will set the appropriate bit in
this command’s result byte only if the Polarity Reversal
Function is enabled for that port.
MJLP Status
Each IMR+ chip contains an independent MAU Jabber
Lock Up Protection Timer. The timer is designed to in-
hibit the IMR+ device transmit function, if it has been
transmitting continuously for more than 65536 Bit
Times. The MJLP Status bit (M) is set to 1 if this
happens. This bit remains set and is only cleared when
the MJLP status is read by using this command.
SI data:
SO data:
SI data:
SO data:
Ln = 0
Ln = 1
SI data:
SO data:
Pn = 0
Pn = 1
SI data:
SO data:
10100000
E7...............E0
11010000
L7...............L0
TP Port n in Link Test Fail
TP Port n in Link Test Pass
11100000
P7...............P0
TP Port n Polarity Correct
TP Port n Polarity Reversed
11110000
M00000000