am79c981 Advanced Micro Devices, am79c981 Datasheet - Page 19

• Manufacturer Part Number: am79c981
• Description: Integrated Multiport Repeater Plus? Imr+? ??9
• Manufacturer: Advanced Micro Devices

Version
This command (1111 1111) can be used to determine
the device version.
The IMR+ chip responds by the bit pattern: XXXX 0001
The IMR chip (Am79C980) responds by the bit pattern:
XXXX 0000
Minimum Mode
The Minimum Mode reconfigures the IMR+ device
Management Port and is intended to provide support for
the low end, non-managed repeaters, requiring minimal
external logic to provide LED indication of:
The Minimum Mode is selected by controlling the state
of the TEST pin while RST is asserted. If TEST is High
(asserted), while reset is active (RST LOW), then Mini-
mum Mode is selected. The state of SI pin, at the
deassertion of the RST signal, determines whether the
IMR+ chip is to be programmed for Automatic Polarity
Detection/Correction.
When entering the Minimum Mode, the TEST input has
to be deasserted on the rising edge of reset. A maximum
delay of 100 ns is allowed to account for slow devices.
The following table summarizes the different modes
available.
Test
Twisted Pair Ports Link Status indication and AUI
Loopback Status
Port Partitioning Status
Twisted Pair Ports Receiver Polarity Status and
AUI SQE Test Error Status
Port Bit Rate Error Status
0
0
1
1
SI data:
SO data:
SI
0
1
0
1
Functions
Normal Management Mode
Normal Management Mode
Minimum Mode, Receive
Polarity Correction disabled
Minimum Mode, Receive
Polarity Correction enabled
11111111
XXXX0001
PRELIMINARY
Am79C981
In Minimum Mode, the SO pin is used to serially output
the various status information based on the state of the
SI and SCLK pins. A summary of the status information
is provided in the following table.
When SI = 0 then SO will output the related AUI status
bits (LoopBack or SQE), followed by the 8 TP status bits
(Link or Polarity), starting with the TP port 0.
When SI = 1, the Port Partitioning Status or Port Bit Rate
Error Status are scanned out with the AUI first and TP
ports following. TP Port 0 is scanned out first.
Note that the Bit Rate Error, AUI Loopback, and AUI
SQE Test Error status bits stay set until they are
scanned out.
The state of SI and SCLK inputs is checked at the end of
every STR cycle. The rising edge of the X1 clock, occur-
ring before falling edge of STR, is used to strobe in the
state of the SI and SCLK pins.
In this Minimum Mode, the Management Port mode is
not active. To exit the Minimum mode, the IMR+ device
must reset into the normal Management Port mode.
SCLK
0
0
1
1
SI
0
1
0
1
SO Output
TP Ports Receive Polarity Status +
AUI SQE Test Error Status.
Bit Rate Error (all ports).
TP Ports Link Status + AUI
LoopBack Status
Port Partitioning Status (all ports)
AMD
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