mh2040 Music Semiconductors, Inc., mh2040 Datasheet - Page 4

• Manufacturer Part Number: mh2040
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

PIN DESCRIPTIONS
Note: Signal names that start with a slash ("/") are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The CAM
architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer to the
Electrical Characteristics section for more information.
DQ31-0 (Data Bus, Three-state, Common
Input/ Output)
The DQ31-0 lines convey data to and from the MH2040.
When the /E input is HIGH the DQ31-0 lines are held in
their high-impedance state. The /W input determines
whether data flows to or from the device on the DQ31-0
lines. The source or destination of the data is determined
by the AC bus, DSC, and the /AV line. During a Write
cycle, data on the DQ31-0 lines is registered by the falling
edge of /E.
AC11-0 (Address/Control Bus, Input)
When Hardware control is selected, the AC bus conveys
address or control information to the MH2040, depending
on the state of the /AV input. When /AV is LOW then the
AC bus carries an address; when /AV is HIGH the AC bus
carries control information. Data on the AC bus is
registered by the falling edge of /E. When software control
is selected, the state of the AC bus does not affect the
operation of the device.
DSC (Data Segment Control, Input)
When DQ bus access to a 64 bit register or memory word
is performed, the DSC input determines whether bits 31-0
(DSC LOW) or bits 63-32 (DSC HIGH) are accessed.
Access to 32 bit registers require that DSC be held LOW.
AA11-0 (Active Address, Output)
The AA bus conveys the Match address, the Next Free
address, or Random Access address, depending on the
most recent memory cycle. The /OE input enables the AA
bus; when the /OE input is HIGH, the AA bus is in its
high-impedance state; when /OE is LOW the AA bus is
active. In a vertically cascaded system after a Comparison
cycle, Write at Next Free Address cycle or Read/Write at
Highest-Priority match, only the highest-priority device
will enable its AA bus, regardless of the state of the /OE
input. In the event of a mismatch in the Address Database
after a Compare cycle, or after a Write at Next Free
Address cycle into an already full system, the
lowest-priority device will drive the AA bus with all 1s.
The AA bus is latched when /E is LOW, and are free to
change only when /E is HIGH.
PA3-0 (Page Address, Output)
The PA3-0 lines convey Page Address information. When
the /OE input is HIGH, the PA3-0 outputs are in their
high-impedance state; when /OE is LOW the PA3-0 lines
carry the Page Address value held in the Configuration
HARRP - HLA Packaged Asynchronous Data Recognition-Recall Processors
4
register. The PA3-0 lines are latched when /E is LOW, and
are free to change only when /E is HIGH. The Page
Address value of the currently active or highest-priority
responding device is output at the same time, and under
the same conditions, as the AA bus is active.
/E (Chip Enable, Input)
The /E input is the main chip enable and synchronizing
control for the MH2040. When /E is HIGH, the chip is
disabled and the DQ31-0 lines are held in their
high-impedance state. The falling edge of /E registers the
/W, /CS1, /CS2, /AV, /AC bus, DSC, and the /VB and
DQ31-0 lines for a Write cycle. /E being LOW causes the
results of the previous comparison or memory access to be
latched on the PA:AA bus; when /E goes HIGH the latches
opens allowing the new comparison results or random
access memory address to flow to the PA:AA bus.
/CS1, /CS2 (Chip Select 1, Chip Select 2,
Inputs)
The /CS1 and /CS2 inputs enable the MH2040. If either
/CS1 or /CS2 are LOW, the device is selected for a Read,
Write, or Compare cycle through the DQ31-0 lines, or for
an internal data transfer. The /CS1 and /CS2 lines do not
have any effect on the PA:AA bus. The state of the /CS1
and /CS2 lines is registered by the falling edge of /E.
/W (Write Enable, Input)
The /W input determines the direction of data transfer on
the DQ31-0 lines during Read, Write, and Data Move
cycles. When /W is LOW, data flows into the DQ31-0
lines; when /W is HIGH, data flows out. The /W line also
conditions the control state present on the AC bus and
DSC lines. The state of the /W line is registered by the
falling edge of /E.
/OE (Output Enable, Input)
The /OE input enables the PA:AA bus. When /OE is
HIGH, PA:AA bus are in their high-impedance state.
When /OE is LOW, PA:AA bus are active, and convey the
results of the last Comparison Cycle Match address or
Memory Access address. In a vertically cascaded system,
only the PA:AA bus of the highest-priority device will be
activated by /OE being LOW; in lower-priority devices,
the PA:AA bus remains in high-impedance regardless of
the state of /OE.
Rev. 1.0