mh2040 Music Semiconductors, Inc., mh2040 Datasheet - Page 9

• Manufacturer Part Number: mh2040
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

OPERATIONAL CHARACTERISTICS
Processor Interface
The processor interface is through a 32-bit data bus
DQ31-0 and control signals comprised of Chip Enable
(/E), two Chip Selects (/CS1, /CS2), Write Enable (/W),
Output Enable (/OE), Validity Bit Control (/VB), Address
Valid (/AV), Data Segment Control (DSC), and
Address/Control inputs (AC bus). When the /AV line is
LOW, the DSC and AC bus carries an address for random
access into the Memory array; when it is HIGH, the AC
bus conveys control information.
Most of the functionality of the MH2040 is accessed
through the control states on DSC and AC bus when /AV
is HIGH. The processor maps the control structure into
memory space and controls the MH2040 through memory
Read and Write cycles. Using this memory mapping
scheme, the /AV line should be driven from logic that
generates a HIGH level within the mapped range of the
control states, and a LOW level outside it. Other control
inputs /E, /W, /CS1, and /CS2 are analogous to SRAM
control inputs.
The /VB line acts like an extra data bit during memory
Read and Write cycles and is used to read and write the
validity of any memory location.
The MH2040 is enabled either through hardware through
/CS1 or /CS2 being LOW, or it is enabled by the value
written to the Device Select register matching with the
Page Address field of the Configuration register. One extra
bit in the Device Select register enables the comparison
between the Page Address value and the Device Select
register. These Chip Select mechanisms operate in
parallel. If any one is active, the device is enabled.
The MH2040 can be controlled directly through software.
The Software Control mode is selected through settings in
the Configuration register.
When the Software Control mode is selected, control
states are written to the Instruction register from DQ8-0
during a Write cycle with the /AV line held HIGH. DQ12
acts as the DSC input. If the control state does not involve
any data transaction on the DQ31-0 lines, the instruction is
executed during the same cycle; the state of DQ13
modifies the instruction, its state is equivalent to the /W
input.
Note: It is up to the system designer to ensure that the correct
cycle type follows the loading of an instruction in Software
Control mode. If the instruction expects a Read cycle, and a
Write cycle is executed, or vice versa, the function of the
MH2040 is undefined. Such an error may lead to data loss, but
will not damage the device physically.
Rev. 1.0
HARRP - HLA Packaged Asynchronous Data Recognition-Recall Processors
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A Read cycle with the /AV line HIGH will access the
Status register, allowing results to be read back without
loading a new instruction. After a Comparison cycle,
Write at Next Free Address cycle or Read/Write at
Highest-Priority match in a vertically cascaded system,
only the highest-priority device will enable its DQ31-0
lines and output the contents of its Status register. After a
Comparison cycle, in the event of a mismatch in the
MU9C, the DQ31-0 lines of the lowest-priority device will
be enabled. After a random access Read or Write cycle,
the Status register of any selected device will be enabled.
Under these circumstances, it is up to the user to ensure
that only a single device is enabled through /CS1, /CS2, or
the Device Select register.
The instruction is persistent, so that all subsequent data
transactions will be executed according to the control state
held in the Instruction register. The results of a
Comparison cycle can be read back from the Status
register, and include PA:AA bus, /MF, /MM, and /FF. The
following sequence of events provides the fastest
operation of the MH2040 in Software Control mode:
/AV
1
0
1
0
1
Operation
Load Compare DQ with CAM’ instruction
Comparand on DQ31-0
Read Status Register
Next Comparand on DQ31-0
Read Status Register, etc.