am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 26

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

not lock the 3-byte receive data FIFO. An SDLC
end-of-frame still locks the 3-byte receive data FIFO in
“Interrupt on first Receive Character or Special Condi-
tion” and “Interrupt on Special Condition Only” modes
when the 10
the 10 19 SDLC FIFO to accept multiple SDLC frames
without CPU intervention at the end of each frame.
FIFO Detail
For a better understanding of details of the FIFO opera-
tion, refer to the block diagram contained in Figure 13.
Enable/Disable
This FIFO is implemented so that it is enabled when
WR15 bit 2 is set and the ESCC is in the SDLC/HDLC
mode, otherwise the status register contents bypass the
FIFO and go directly to the bus interface (the FIFO
pointer logic is reset either when disabled or via a chan-
nel or power-on reset). When the FIFO mode is dis-
abled, the ESCC is completely downward-compatible
with the NMOS Am8530. The FIFO mode is disabled on
power-up (WR15 bit 2 is set to 0 on reset). The effects of
backward compatibility on the register set are that RR4
is an image of RR0, RR5 is an image of RR1, RR6 is an
image of RR2, and RR7 is an image of RR3. For the de-
tails of the added registers, refer to Figure 15. The status
of the FIFO Enable signal can be obtained by reading
RR15 bit 2. If the FIFO is enabled, the bit will be set to 1;
otherwise, it will be reset.
Read Operation
When WR15 bit 2 is set and the FIFO is not empty, the
next read to status register RR1 or the additional regis-
ters RR7 and RR6 will actually be from the FIFO. Read-
ing status register RR1 causes one location of the FIFO
to be emptied, so status should be read after reading the
byte count, otherwise the count will be incorrect. Before
the FIFO underflows, it is disabled. In this case, the mul-
tiplexer is switched to allow status to be read directly
26
Data Stream
AMD
Byte Count
F : Flag
A : Address Field
D : Data
C : Control Field
Key
19 FIFO is disabled. This feature allows
0
F
Don’t Load
Counter On
1st Flag
Reset Byte
Counter Here
A D D D D C C F
1 2 3 4 5 6 7
Internal Byte Strobe
Increments Counter
Figure 14. SDLC Byte Counting Detail
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
Am85C30
from the status register, and reads from RR7 and RR6
will contain bits that are undefined. Bit 6 of RR7 (FIFO
Data Available) can be used to determine if status data
is coming from the FIFO or directly from the status regis-
ter, since it is set to 1 whenever the FIFO is not empty.
Because not all status bits are stored in the FIFO, the All
Sent, Parity, and EOF bits will bypass the FIFO. The
status bits sent through the FIFO will be Residue Bits
(3), Overrun, and CRC Error.
The sequence for proper operation of the byte count and
FIFO logic is to read the registers in the following order,
RR7, RR6, and RR1 (reading RR6 is optional). Addi-
tional logic prevents the FIFO from being emptied by
multiple reads from RR1. The read from RR7 latches the
FIFO empty/full status bit (bit 6) and steers the status
multiplexer to read from the SCC megacell instead of
the status FIFO (since the status FIFO is empty). The
read from RR1 allows an entry to be read from the FIFO
(if the FIFO was empty, logic is added to prevent a FIFO
underflow condition).
Write Operation
When the end of an SDLC frame (EOF) has been re-
ceived and the FIFO is enabled, the contents of the
status and byte-count registers are loaded into the
FIFO. The EOF signal is used to increment the FIFO. If
the FIFO overflows, the MSB of RR7 (FIFO Overflow) is
set to indicate the overflow. This bit and the FIFO control
logic are reset by disabling and reenabling the FIFO
control bit (WR15 bit 2). For details of FIFO control tim-
ing during an SDLC frame, refer to Figure 14.
Byte Counter Detail
The 14-bit byte counter allows for packets up to 16K
bytes to be received. For a better understanding of its
operation, refer to Figures 13 and 14.
0
F
Reset
Byte Counter
1 2 3 4 5 6 7
A D D D D C C F
Internal Byte Strobe
Increments Counter
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
10216F-18