am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 9

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

ARCHITECTURE
The ESCC internal structure includes two full-duplex
channels, two 10
FIFOs, two baud rate generators, internal control and in-
terrupt logic, and a bus interface to a non-multiplexed
bus. Associated with each channel are a number of
Read and Write registers for mode control and status in-
formation, as well as logic necessary to interface with
modems or other external devices (see Logic Symbol).
The logic for both channels provides formats, synchroni-
zation, and validation for data transferred to and from
the channel interface. The modem control inputs are
monitored by the control logic under program control. All
of the modem control signals are general-purpose in na-
ture and can optionally be used for functions other than
modem control.
The register set for each channel includes ten control
(Write) registers, two SYNC character (Write) registers,
and four status (Read) registers. In addition, each baud
rate generator has two (Read/Write) registers for hold-
ing the time constant that determines the baud rate. Fi-
nally, associated with the interrupt logic is a Write
register for the interrupt vector accessible through either
channel, a Write-only Master Interrupt Control register,
Control
Data
8
5
+5 V GND PCLK
19 bit SDLC/HDLC frame status
Bus VO
Interrupt
CPU
Control
Lines
Figure 1. Block Diagram of ESCC Architecture
Interrupt
Internal
Control
Control
Logic
Logic
Internal Bus
Registers
Channel
Registers
Channel
Am85C30
A
B
and three Read registers: one containing the vector with
status information (Channel B only), one containing the
vector without status (A only), and one containing the in-
terrupt pending bits (A only).
The registers for each channel are designated as
follows:
WR0–WR15—Write Registers 0 through 15. An addi-
tional Write register, WR7 Prime (WR7 ), is available for
enabling or disabling additional SDLC/HDLC enhance-
ments if bit D
RR0–RR3, RR10, RR12, RR13, RR15—Read Regis-
ters 0 through 3, 10, 12, 13, and 15.
If bit D
ters, RR6 and RR7, are available. These registers are
used with the 10
Table 1 lists the functions assigned to each Read
and Write register. The ESCC contains only one
WR2 and WR9, but they can be accessed by either
channel. All other registers are paired (one for
each channel).
2
of WR15 is set, then two additional Read regis-
0
Generator
10 19 Bit
Channel A
of WR15 is set.
Baud
Frame
Status
Rate
FIFO
19 bit Frame Status FIFO.
Channel B
Transmitter
Receiver
Control
Logic
TxDA
RxDA
RTxCA
TRxCA
SYNCA
RTSA
CTSA
DCDA
TxDB
RxDB
RTxCB
TRxCB
SYNCB
RTSB
CTSB
DCDB
10216F-5
AMD
9