am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 37

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

whereas bit D
able and enable by just forcing the TxD pin High when
set even though the transmitter may actually be mark or
flag idling. Care must be used when setting this bit be-
cause any character being transmitted at the time this bit
is set will be “chopped off,” and data written to the Trans-
mit Buffer while this bit is set will be lost.
When the transmit underrun occurs and the CRC and
closing flag have been sent, bit D
High. When ready to start sending data again this bit
must be reset to 0 before the first character is written to
the Transmit Buffer. Note that resetting this bit causes
the TxD pin to take whatever state the NRZI encoder is
in at the time, so synchronization at the receiver may
take longer because the first transition seen on the TxD
pin may not coincide with a bit boundary. Note that in or-
der for this to function properly, bits D
must be set to 1 and 0, respectively.
Interrupt Masking Without INTACK
The NMOS Am8530H’s ability to mask lower priority in-
terrupts is done via the IUS bit. This bit is internal to the
SCC and is not observable by the processor. Being able
to automatically mask lower priority interrupts allows a
modular approach to coding interrupt routines. How-
ever, using the masking capabilities of the NMOS SCC
requires that the INTACK cycle be generated. In stand-
alone applications, having to generate INTACK through
external hardware in order to use this capability is an
unnecessary expense.
On the CMOS Am85C30, if bit D
INTACK cycle does not need to be generated in order to
have the IUS bit set. This allows the user to respond to
ESCC interrupt requests with a software acknowledg-
ment through RR2. When bit D
3
of WR7 acts as a pseudo transmitter dis-
Figure 18. Transmitter Disabling with NRZI Encoding
Transmitter Disabled Here
TxD Pin Output (NRZI Encoded)
5
Lo
5
Hi
3
in WR9 is set and an
in WR9 is set to 1, the
can be set to pull TxD
3
and D
1 1 0
2
of WR10
Am85C30
0
1
interrupt occurs, a read to RR2 emulates a hardware
Interrupt Acknowledge cycle as it functions in Vectored
mode. In this case the CPU must first read RR2 to deter-
mine the internal interrupt source and then jump to the
appropriate interrupt routine. Reading RR2 sets the IUS
bit for the highest priority IP. After the interrupting condi-
tion is cleared, the routine can then read RR3 to deter-
mine if any other IPs are set and clear them. At the end
of the interrupt routine, a Reset IUS command must be
issued to unlock the internal daisy chain.
Since the CPU can acknowledge the ESCC of highest
priority with a read of its RR2 interrupt vector, there is no
need for an external daisy chain. IEI for all ESCC de-
vices should be tied active High. When acknowledging
an ESCC interrupt request, the CPU must issue one
read to RR2 per interrupt request. The modified inter-
rupt vector can be read from Channel B, or the original
vector stored in WR2 can be read from Channel A.
Either action will produce the same internal actions on
the IUS logic. Note that the No Vector and Vector In-
cludes Status bits in WR9 are ignored when bit D
WR9 is set to 1.
2-Mb/s FM Data Transmission and
Reception
The 16-MHz version of the CMOS Am85C30
(Am85C30-16) is capable of transmitting and receiving
FM-encoded data at the rate of 2 Mb/s. This is accom-
plished by applying a 32-MHz clock to the RTxC pin and
assigning this waveform to drive the Internal Digital
Phase-Locked Loop (DPLL) clock. This feature allows
the user to send both clock and data information over
the same line at 2 Mb/s and can eliminate external
DPLLs required for high-speed NRZ data clock
generation.
1
1
1
1
1 0
0
10216F-22
AMD
5
37
in