hi-3596 Holt Integrated Circuits, Inc., hi-3596 Datasheet
hi-3596
Related parts for hi-3596
hi-3596 Summary of contents
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... The SPI and all control signals are CMOS and TTL compatible and support 3. operation. The HI-3596 and HI-3598 are full featured parts. The HI-3597 and HI-3599 give the user the option of utilizing a smaller 24-pin SOIC package with very little trade off in features. In this case, a global interrupt fl ...
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... Kohm BUS 3 RIN1A { BUS 2 40 Kohm RIN1B ARINC 429 Bus 1 RIN1A-40 RIN1B-40 NOTE: RIN1A & RIN1B available only on HI-3596 RIN1A-40 & RIN1B-40 available only on HI-3596-40 HI-3597 & HI-3599 (24-pin versions) ACLK SCK CS SPI Interface SI SO Transmit Register TX1, TX0 (HI-3597 only ...
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... TX0 OUTPUT ARINC 429 test word ZERO state serial output pin MR INPUT * NOTE: RIN1A & RIN1B are not available on HI-3597 HI-3596, HI-3597, HI-3598, HI-3599 Table 1. Pin Descriptions 3.3V or 5.0V power supply Chip 0V supply Chip select. Data is shifted into SI and out of SO when CS is low SPI Clock ...
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... HI-3596, HI-3597, HI-3598, HI-3599 INSTRUCTIONS Instruction op codes are used to read, write and con- fi gure the HI-359x devices. The instruction format is illustrated in Figure 2. When CS goes low, the next 8 clocks at the SCK pin shift an instruction op code into the decoder, starting with the fi rst rising edge. The op code is fed into the SI pin, most signifi ...
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... HI-3596, HI-3597, HI-3598, HI-3599 FUNCTIONAL DESCRIPTION Control Word Register Each HI-359x receive channel is assigned a 16-bit Control Register which confi gures that receiver. Con- trol Register bits CR15 - CR0 are loaded from a 16-bit data value appended to SPI instruction n4 hex, where “n” is the channel number 1-8 hex. Writing to the Con- trol Register also clears the data FIFO for that channel ...
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... HI-3596, HI-3597, HI-3598, HI-3599 ARINC 429 Data Format Control Register bit CR9 controls how individual bits in the received ARINC word are mapped to the HI-359x SPI data word during data read operations. Table 5 describes this mapping. Table 5. SPI / ARINC bit-mapping SPI / ARINC bit-mapping ...
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... HI-3596, HI-3597, HI-3598, HI-3599 SCK FLAG FIFO LOAD CONTROL / CONTROL BITS CR2, CR6-8 16-label Memory EOS ONES SHIFT REGISTER NULL SHIFT REGISTER ZEROS SHIFT REGISTER The HI-359x family accept signals within these toler- ances and rejects signals outside these tolerances. ...
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... HI-3596, HI-3597, HI-3598, HI-3599 3. To validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. With exactly 1MHz input clock frequency, the acceptable data bit rates are shown in Table 8. ...
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... Status Register FIFO fl ags and FIFO status output signals are also cleared. Master Reset does not affect the eight channel Control Registers. Master Reset may be asserted using the MR input pin (HI-3596 and HI-3598 only executing SPI instruction n7 hex. An individual receive channel can be reset by setting its corresponding Control Register CR3 bit to “ ...
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... HI-3596, HI-3597, HI-3598, HI-3599 TIMING DIAGRAMS CS t CHH SCK SCKH SCKL SCK SO Hi Impedance ARINC DATA BIT 31 BIT 32 FLAG t RFLG CS SCK SI SO SERIAL INPUT TIMING DIAGRAM t CES t t SCKR DH MSB SERIAL OUTPUT TIMING DIAGRAM t DV MSB RECEIVER OPERATION ...
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... HI-3596, HI-3597, HI-3598, HI-3599 ABSOLUTE MAXIMUM RATINGS Supply Voltages V ...................................................... -0.3 to +7.0V DD Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ........... -29V to +29V Voltage at any other pin ......................................... -0. Solder temperature (Leads) ............................ 280 (Package) .................................................... 220 NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. ...
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... HI-3596, HI-3597, HI-3598, HI-3599 Parameters Output Current (All outputs and Bi- directional pins) Output Capacitance OPERATING VOLTAGE RANGE OPERATING SUPPLY CURRENT VDD = 3.3V or 5.0V, GND = 0V Operating Temperature Range and f A Parameters SPI INTERFACE TIMING SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge ...
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... HI-3596, HI-3597, HI-3598, HI-3599 HEAT SINK - CHIP SCALE PACKAGE (QFN) ONLY The HI-3596PCx, HI-3598PCx, and HI3599PCx use 44-pin or 64-pin plastic chip-scale (QFN) packages. These pack- ages have a metal heat sink pad on the bottom surface that is electrically connected to the die. For these receivers, small size is the primary advantage of this package style. Heat sinking provides little benefi ...
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... HI-3596, HI-3597, HI-3598, HI-3599 HI-3599PCx - HI-3599PCI - 6 HI-3599PCT - 7 RIN1A - 8 RIN1B - 44-Pin Plastic 7mm x 7mm Chip-Scale Package (QFN) HI-3599PSx ACLK - VDD SCK - FLAG RIN8B HI-3599 RIN8A PSI 20 - RIN7B RIN1A - RIN7A & RIN1B - RIN6B ...
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... HI-3596, HI-3597, HI-3598, HI-3599 ORDERING INFORMATION (HI-3598 all pins 3598 PART NUMBER Blank PART NUMBER PART NUMBER PC PQ ORDERING INFORMATION (HI-3596 HI - 359x Not available in PSx package Not available in PCx package. LEAD FINISH Tin / Lead (Sn / Pb) Solder F 100% Matte Tin (Pb-free, RoHS compliant) ...
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... HI-3596, HI-3597, HI-3598, HI-3599 REVISION HISTORY Revision Date DS3598, Rev. NEW 6/12/08 Rev. A 5/22/09 Rev. B 11/23/09 Description of Change Initial Release. Clarifi ed relationship between SPI bit order and ARINC 429 bit order. Corrected typo on receivers pin nomenclature on page 3. Added and updated Figure and Table cross-references. Condensed Control and Status Register tables. Corrected minor typos. Clarifi ...
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... HI-3596, HI-3597, HI-3598, HI-3599 PACKAGE DIMENSIONS 52-PIN PLASTIC QUAD FLAT PACK (PQFP) .520 BSC SQ (13.2) See Detail A .063 MAX. (1.6) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) .354 BSC (9.00) .354 ...
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... HI-3596, HI-3597, HI-3598, HI-3599 24-PIN PLASTIC SMALL OUTLINE (SOIC (Wide Body) .407 ± .013 (10.325 ± .32) .050 BSC (1.27) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) Top View ...