hi-3596 Holt Integrated Circuits, Inc., hi-3596 Datasheet - Page 7

• Manufacturer Part Number: hi-3596
• Description: Octal Arinc 429 Receivers With Label Recognition And Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

The HI-359x family accept signals within these toler-
ances and rejects signals outside these tolerances.
Receiver logic achieves this as described below:
1. An accurate 1MHz clock source is required to vali-
2. The receiver uses three separate 10-bit sampling
CONTROL BITS
date the receive signal timing. Less than 0.1% error
is recommended.
shift registers for Ones detection, Zeros detection
and Null detection. When the input signal is within
the differential voltage range for any shift register’s
state (One Zero or Null) sampling clocks a high bit
into that register. When the receive signal is outside
the differential voltage range defi ned for any shift
register, a low bit is clocked. Only one shift register
can clock a high bit for any given sample. All three
CR2, CR6-8
FLAG
ZEROS
ONES
NULL
CONTROL
LOAD
FIFO
EOS
16-label
Memory
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
SCK
CS
SO
SI
/
HI-3596, HI-3597, HI-3598, HI-3599
COMPARE
DECODE
LABEL /
32-BIT SHIFT REGISTER
Figure 4. Receiver Block Diagram
HOLT INTEGRATED CIRCUITS
SPI INTERFACE
4 words x 32-bit
FIFO
7
WORD GAP
BIT CLOCK
DATA
START
registers clock low bits if the differential input volt-
age is between defi ned state voltage bands.
Valid data bits require at least three consecutive
One or Zero samples (three high bits) in the upper
half of the Ones or Zeros sampling shift register, and
at least three consecutive Null samples (three high
bits) in the lower half of the Null sampling shift regis-
ter within the data bit interval.
A word gap Null requires at least three consecutive
Null samples (three high bits) in the upper half of the
Null sampling shift register and at least three con-
secutive Null samples (three high bits) in the lower
half of the Null sampling shift register. This guaran-
tees the minimum pulse width.
PARITY
CHECK
SEQUENCE
WORD GAP
CONTROL
DETECTION
ERROR
TIMER
32ND
BIT
END
ERROR
CLOCK
BIT CLOCK
SEQUENCE
COUNTER
END OF
AND
BIT
ACLK